9,878 research outputs found
A full chip scale numerical simulation method for thermal management of 3D IC
No full textThermal issue is becoming more and more serious when integrated circuits (IC) further explores along the road of More Moore with dramatic increments of integration degree and power density. Thermal management, including thermal design, modeling, and optimization, has been an important concern in the system-level design of 3D IC. Current thermal modeling for a system level 3D IC design usually relies on a simplified thermal resistance network, which requires trade-offs between the model complexity and the simulation accuracy. Comparing to traditional thermal resistance based model, finite element simulation can provide a more accurate simulation for the thermal management of 3D IC. However, a full chip scale numerical simulation is still lack as an unacceptable huge grid number is unavoidable to deal with the geometric size mismatch existed in a 3D IC. Moreover, current finite element method based numerical simulation tools have no direct supports for the thermal management of 3D IC, since the placement design usually consists a complex data structure from a 3D IC. A method to bridge the finite element method and the 3D IC placement is introduced in this work. The whole bridge process includes placement data structure extraction, 3D IC system model generation, structure, mesh, solver configuration, calculation, and post data analysis. A full chip scale numerical simulation was demonstrated based the present bridge method along with the recently reported equivalent thermal conductivity simplified model.CPCI-S(ISTP)[email protected]; [email protected]
The driving force for development of IC and system in future: Reducing the power consumption and improving the ratio of performance to power consumption
No full textWith the development of information technology, integrated circuits (IC) and system which target high performance and low power consumption have widely penetrated to all the aspects of national economy, national defense construction and people's life. With the continuous increase in IC integration density, the power consumption is becoming the limiting factor. It turns out that the driving force of the future IC and system development is the reduction of the power consumption and improvement of the performance/power ratio. The Moore's Law is inherently the law for the technology and economic development, and has served as the guideline of the IC development for half a century. However, with the scaling down of IC feature size and the corresponding increased integration density, it is progressively approaching the physical limitation. Moore's Law will gradually complete its historic mission and it will be replaced by a law of reducing the power consumption while ensuring the performance requirements for IC, SoC and SiP performance, law of improving the performance/power ratio. This paper will discuss the related research topics on Green micro/nanoelectronics, including low-power design, novel low-power devices, manufacturing processes for low power applications and related micro/nano electromechanical systems.Computer Science, Information SystemsSCI(E)5ARTICLE5,SI915-9355
A Study on the Application of Fuzzy Analytic Hierarchy Process to IC Industrial Policy Adoption
No full textAfter decades of development, Taiwan\ue2s IC industry has become the world\ue2s third largest manufacturing center, and claimed the positions of the world\ue2s first largest IC foundry industry, second largest packaging industry, as well as second largest IC design industry. For an industry to be successful, in addition to the provision of various niches and resources from private businesses, it requires the coordination of industrial policy-making, peripheral conditions, and infrastructures. Therefore, to enhance current competitive advantages and facilitate industrial transformation for greater competitiveness, the government needs to make effective industrial policy to promote competitive environment. For this reason, this study intends to investigate the current competitive environment of IC industry, how the government responds in terms of stipulating rules and regulations, and what the primary concerns of policy adoption are. It is clear that aside from an effort by businesses, the assistance from government is pivotal to industrial development as well.
This study is an attempt to first, collect literature related to industrial analysis and policy; secondly, to analyze the competitive environment of IC industry and thereby find out the relevant policies that influence the managerial effectiveness of Taiwan\ue2s IC industry; and lastly, to survey IC companies and experts on IC industry by utilizing a questionnaire designed based on Fuzzy Analytic Hierarchy Process. After prioritizing the concrete measures for a variety of dimensions of IC industrial policies based on the survey results, the researcher proposes top ten most emphasized including: the assistance in introduction of techniques, the training of technological talented, the aid in the development of SOC technique, the subsidy in R&D of innovative techniques, the accelerated depreciation on R&D equipments, the implementation of three-links, the tariff exemption for importing R&D equipments, the enhancement of National Defense Substitute Servicemen (NDSS), the training of marketing talented, and the enactment of patent rules. Accordingly, this study concluded by providing suggestions for government, IC industry, and future research
Implementation of a customizable GUI software platform for IC equipment
No full textWith the development of semiconductor industry, different types of wafer processing are increasing. According to the different wafer processing models, the need of data display and process is different. In this paper, a customizable software platform is described for the manufacturing equipment of semiconductor integrated circuit (IC equipment). The C# control technology has been used to build the IC equipment customizable control system interface. The development method of customizable control technology based on C# can realize the control of the reuse and codes sharing, in order to improve programming efficiency, avoid the development of two times, cost saving and be easy to debug
A 0.6V 3.8μW ECG/bio-impedance monitoring IC for disposable health patch in 40nm CMOS
No full text Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular and respiratory diseases. However, a sensing IC must consume ultra-low power under a sub-volt supply to comply with miniaturized and disposable batteries. This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC. The AFE can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme. To ensure the IA can tolerate up to 300mVpp DC electrode offset and 400mV pp common-mode (CM) interference, a DC-servo loop (DSL) combined with a common-mode feedforward (CMFF) loop is employed. A buffer-assisted scheme boosts the IA's input impedance by 7x to 140MΩ at 10Hz. To improve the BioZ sensitivity, the CG utilizes dynamic element matching to reduce the 1/f noise of the output current, leading to 35mΩ/√Hz BioZ sensitivity down to 1Hz. The ADC shows a 9.7b ENOB when sampled at 20ksps. The total power consumption of the AFE is 3.8μW. Bio-Electronic
IC-MAC: A dynamic scheduling supported MAC protocol optimized for intra-cluster communication
No full textCluster-based architecture is a widely and deeply studied network architecture used in wireless sensor networks. With enough available channels and proper channel assignment policy, clusters using the same channel can be separated distant enough to avoid interference from each other. In each such cluster, the traffic demand usually exists only between the cluster head and the end nodes. We refer to such kind of communication pattern as "Independent intra-cluster communication (IICC)" pattern. In this paper we present IC-MAC, a MAC protocol specifically optimized for such a communication pattern. IC-MAC is a variant of IEEE 802.15.4 and it introduces a dynamic scheduling mechanism into the superframe structure of 802.15.4. With this mechanism, IC-MAC uses the slotted CSMA/CA algorithm under low network load, and can automatically switch to schedule-based transmission when the load becomes high. Simulation results show that the performance of IC-MAC exceeds IEEE 802.15.4 overwhelmingly under the IICC pattern, and the advantage is especially obvious under high network load
BIST methodology, architecture and circuits for pre-bond TSV testing in 3D stacking IC systems
No full text© 2004-2012 IEEE. This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction
No full textThis article presents the first keyword spotting (KWS) IC that uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front end. Benefiting from fundamental building blocks based on digital logic gates, it offers better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65-nm CMOS process, the prototyped KWS IC occupies 2.03 mm 2 and dissipates 23- power consumption, including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves a 54.89-dB dynamic range for 16-ms frame shift size while consuming 9.3 . The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command dataset (GSCD) with >86% accuracy and 12.4-ms latency. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic
A 1024-Channel 268 nW/pixel 36x36 μm<sup>2</sup>/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces
No full textThis paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 μ m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 μ VRMS input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Bio-Electronic
Security Enhancement of an IC-Card-Based Remote Login Mechanism
Full text link[[abstract]]Wang et al. presented a remote password authentication scheme using IC (Integrated Circuit) cards in 2004. Unfortunately, we discovered that their scheme is unable to withstand the forgery attack. We consequently propose in this paper a novel version to resist this kind of attacks. Furthermore, our scheme can also provide mutual authentication between a remote server and login users. The security of our scheme is based on the public one-way hash function. What is more, the timestamp mechanism is applied in our scheme to protect such potential attacks in the case that an intruder may replay a previously intercepted login request to access the remote server
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