654 research outputs found
Thermal analysis of effects of high intensity laser beam on biological tissue using FEM by Viswanathan Subramanian
No full textManaging the Impact of On-chip Temperature on the Lifetime Reliability of Reliably Overclocked Systems
Get PDFPhysical and environmental variations require the addition of safety margins to the clock frequency of digital systems, making it overly conservative. Aggressive, but reliable, dynamic clock frequency tuning mechanisms that achieve higher system performance, by adapting the clock rates beyond worst case limits, have been proposed earlier. Even though reliable over-clocking guarantees functional correctness, it leads to higher power consumption and overheating. As a consequence, reliable over-clocking without considering on-chip temperatures will bring down the lifetime reliability of the chip. In this paper, we analyze how reliable over-clocking impacts the on-chip temperature of microprocessors, and evaluate the effects of overheating, due to reliable dynamic over-clocking mechanisms, on the lifetime reliability of such systems. We, then, evaluate the effects of performing thermal throttling, a technique that clamps the on-chip temperature below a predefined value, on system performance and reliability. Our study shows that a reliably over-clocked system, along with dynamic thermal throttling, achieves around 25% performance improvement, while operating within 355 K.This is a manuscript of a proceeding published as Subramanian, Viswanathan, Prem Kumar Ramesh, and Arun K. Somani. "Managing the impact of on-chip temperature on the lifetime reliability of reliably overclocked systems." In 2009 Second International Conference on Dependability (2009): DOI: 10.1109/DEPEND.2009.30. Posted with permission.</p
Conjoined Processor: A Fault Tolerant High Performance Microprocessor
Get PDFReliability has become a serious concern as systems embrace nanometer technologies. Current reliability enhancement techniques cause slowdown in processor operation. In this work, we propose a novel approach that organizes redundancy in a special way to provide high degree of fault tolerance. Our approach improves performance by reliably adapting the system clock frequency during run time, based on the current running application and environmental conditions. The organization of redundancy in the proposed conjoined processor supports overclocking, provides concurrent error detection and recovery capability for soft errors, timing errors, intermittent faults and detects silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Post-layout timing annotated gate level simulations of a conjoined two stage arithmetic pipeline shows that our approach achieves near 100% fault coverage, and a performance improvement of 21%. A five stage in-order conjoined pipeline processor was designed and implemented to verify correctness of the proposed architecture.This is a manuscript of the presentation Subramanian, Viswanathan, Naga D. Avirneni, and Arun K. Somani. "Conjoined processor: a fault tolerant high performance microprocessor." 2008 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2008), March 26-27, 2008, Austin, TX. Posted with permission.</p
An Unsung Hero of the Tanner--Jeffrey Subramanian
Get PDFJeffrey Subramanian beautifies the grounds surrounding the Tanner Building, but he also writes poetry and plays the cello. The author calls Jeffrey an unsung hero because he is, in fact, the author\u27s hero
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Get PDFSynchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.This is a manuscript of a proceeding published as Subramanian, Viswanathan, Mikel Bezdek, Naga D. Avirneni, and Arun Somani. "Superscalar processor performance enhancement through reliable dynamic clock frequency tuning." In 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), (2007): 196-205. DOI: 10.1109/DSN.2007.90. Posted with permission.</p
SEU Mitigation Techniques for Microprocessor Control Logic
Get PDFThe importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance devices and embedded processors. System level solutions to the challenge of fault tolerance flag errors and utilize penalty cycles to recover through the re-execution of instructions. This motivates the need for a hybrid technique providing fault detection as well as fault masking, with minimal penalty cycles for recovery from detected errors. We propose three architectural schemes to protect the control logic of microprocessors against single event upsets (SEUs). High fault coverage with relatively low hardware overhead is obtained by using both fault detection with recovery and fault masking. Control signals are classified as either static or dynamic, and static signals are further classified as opcode dependent and instruction dependent. The strategy for protecting static instruction dependent control signals utilizes a distributed cache of the history of the control bits along with the triple modular redundancy (TMR) concept, while the opcode dependent control signals are protected by a distributed cache which is used to flag errors. Dynamic signals are protected by selective duplication of datapath components. The techniques are implemented on the OpenRISC 1200 processor. Our simulation results show that fault detection with single cycle recovery is provided for 92% of all instruction executions. FPGA synthesis is performed to analyze the associated cycle time and area overheads.This is a manuscript of a proceeding published as Ganesh, T. S., Viswanathan Subramanian, and Arun Somani. "SEU Mitigation Techniques for Microprocessor Control Logic." In 2006 Sixth European Dependable Computing Conference (2006): 77-86. DOI: 10.1109/EDCC.2006.21. Posted with permission.</p
Soft Error Mitigation Schemes for High Performance and Aggressive Designs
Get PDFIn this paper, we address the issue of soft errors in random logic and develop solutions that provide fault tolerance capabilities without logic duplication. First, we present a circuit level soft error mitigation technique which allows systems to operate without the performance overhead of soft error detection and correction circuitry. This is achieved by sampling data using our Soft Error Mitigation (SEM) register cell, which uses a distributed and temporal voting scheme for soft error detection and correction. Next, we present a scheme to concurrently detect and correct soft and timing errors using a Soft and Timing Error Mitigation (STEM) register cell, which offers soft error protection in aggressive designs that allow overclocking. Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier circuit and five-stage DLX processor show that both of our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a temporal Triple Modular Redundancy (TMR) voter based register cell, while STEM outperforms SEM by 27.42%.This is a manuscript of the presentation Avirneni, Naga Durga Prasad, Viswanathan Subramanian, and Arun K. Somani. "Soft error mitigation schemes for high performance and aggressive designs." 2009 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2009). March 24-25, 2009, Stanford, CA. Posted with permission.</p
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems
Get PDFThe threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely soft error mitigation (SEM) and soft and timing error mitigation (STEM), for protecting combinational logic blocks from soft errors. Our first technique (SEM), based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock generation scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45 nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation scheme, while STEM outperforms SEM by 27.42%.This is a manuscript of a proceeding published as Avirneni, Naga Durga Prasad, Viswanathan Subramanian, and Arun K. Somani. "Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems." In 2009 IEEE/IFIP International Conference on Dependable Systems & Networks (2009): 185-194. DOI: 10.1109/DSN.2009.5270340. Posted with permission.</p
Multiscale damage in co-cured composites - Perspectives from experiments and modelling
No full textBonded and co-cured composites are popular alternatives to structures joined with mechanical fasteners in aircraft but the complex and coupled damage mechanisms in the co-cured/bonded region are poorly understood, thus making the evaluation of their strength and durability difficult with current modelling strategies. This study explores the potential of interleaf inclusion in failure-prone, critical regions of co-cured composite specimens in improving the joint strength and interface fracture toughness and strives to advance the understanding of damage initiation in the co-cured region using an atomistic model. A two-pronged approach is pursued here with bench-scale experimental testing and molecular modelling in this study. Experiments are performed for mode I fracture toughness with double cantilever beam (DCB) on composite laminates with an epoxy interleaf layer. Two epoxy resins and three methods for interleaf inclusion are explored in this study; we supplement the results from DCB testing with insights from confocal microscopy on the crack tip and the interleaf layer pre- and post-testing. Molecular dynamic (MD) simulations capture the cohesive interactions at the threephase interface containing the carbon fiber, the prepreg epoxy, and the interleaf epoxy. Results highlight that an interleaf layer made from partially-cured and filmed epoxy, further consolidated in the composite lay-up is the most effective way to suppress void formation, improve dispersion, and maximize cohesive interactions at the interface of co-cured composites.Aerospace Structures & Computational Mechanic
Bol Processor BP2
No full textBol Processor 2 (BP2) is a music composition/improvisation software producing arrangements of sound-objects with a set of rules similar to formal grammars. The inference engine produces strings of symbols feeding an algorithm for the expansion of (polymetric) polyphonic/polyrhythmic structures, and ultimately a time-setting algorithm dealing with constraints on sound-objects. First interfaced with MIDI and Csound, BP2 has a great potential for modelling durations and melodic patterns in speech synthesis.Link on SourceForge: http://bolprocessor.sourceforge.netBol Processor 2 (BP2) es uno software de composición y improvisación de música producir arreglos de sonido de objetos con un conjunto de normas similares a las gramáticas formales. El motor de inferencia produce cadenas de símbolos que alimente un algoritmo para la expansión de (polimétrico) polifónicos/polirrítmica estructuras, y en última instancia, un algoritmo de establecimiento de tiempo de hacer frente a las limitaciones en el sonido-objetos. En primer lugar interconectado con MIDI y Csound, BP2 tiene un gran potencial para el modelado de las duraciones y los patrones melódicos en la síntesis de voz.Enlace en SourceForge: http://bolprocessor.sourceforge.netBol Processor 2 (BP2) est un logiciel de composition/improvisation générant des structures d'objets sonores à partir d'un ensemble de règles similaires à celles des grammaires formelles. Le moteur d'inférence produit des chaînes de symboles auxquelles sont appliquées un algorithme d'expansion de structures polyphoniques/polyrythmiques (polymetriques), puis un algorithme de temporalisation utilisant des contraintes sur les objets sonores. Interfacé à l'origine avec MIDI et Csound, BP2 peut être utilisé pour modéliser les durées et les formes mélodiques en synthèse de la parole.Lien sur SourceForge : http://bolprocessor.sourceforge.netBEL, B. Acquisition et représentation de connaissances en musique. Thèse de Doctorat en Sciences (nouveau régime) : Université de Droit, d'Economie et des Sciences d'Aix-Marseille III. Sous la direction de M. Alain Guénoche. Novembre 1990. Paris: EDILIVRES. 2008http://tel.archives-ouvertes.fr/tel-0000969
- …
