1,720,962 research outputs found
Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit
No full textA new radix-3 partitioning method of natural
numbers, derived by the weight partition theory, is employed to
build a multiplier-less circuit well-suited for multimedia filtering
applications. The partitioning method allows to conveniently pre-
multiply 32 bit floating-point (FP32) filter coefficients with the
smallest set of parts composing an unsigned integer input. In this
way, similarly to the Distributed Arithmetic, shifters and
recoding circuitry, typical of other well-known multiplier
circuits, are completely substituted with simplified floating-point
adders. Compared to the existent literature, targeted to both
FPGA and std_cell technology, the proposed solution achieves
state-of-the-art performances in terms of elaboration velocity,
achieving a critical path delay of about 2 ns both on a Xilinx
Virtex 7 and with CMOS 90nm std_cells
SASCr3: A Real Time Hardware Coprocessor for Stereo Correspondence
No full textMain focus of this paper is to show the relevant improvements for a real time hardware co-processor for Stereo-Matching. The approach follows the well-known scheme for strings alignment proposed by Needleman&Wunsch, commonly used in bio-informatics. The principal improvement concerns the algorithm parallelization in FPGA design, in an hardware architecture many resources can work at the same time avoiding the reduction of system performance. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. For many parallelism degrees the synthesis and performance results are shown, for this purpose a Lattice ECP3-70 is set as target device. The aim of this project is to build stereo vision system for embedded application, charaterized by low power usage and device cost. The actual circuit is an updated version of SASCr2 design. Performance is benchmarked against the former implementation
CDVS: STM Detector Hw accelerator feasibility study and demonstrator
No full textIn order to validate feasibility of HW acceleration for interest point detection, one of the most computational intensive part of the CDVS pipeline, STM has designed and implemented on FPGA a draft HW accelerator IP and demonstration is provided
SASCr2: Enhanced hardware string alignment coprocessor for stereo correspondence
No full textIn this paper new and significant improvements for a recently proposed hardware co-processor for Stereo Matching are introduced. Main focus is on small memory requirements while preserving the needed accuracy. Starting from a pair of stereo images, the co-processor computes the “disparity map” used to define corresponding points on the two images. The approach follows the well-known scheme for string alignment by Needleman & Wunsch, commonly used in bioinformatics. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. Synthesis results for several FPGA platforms are shown. The actual circuit is an updated version of SASC design. Performance is benchmarked against the former implementation as well as against two reference software versions
SASC: A hardware string alignment coprocessor for stereo correspondence2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA)
No full textIn this paper a design scheme is proposed for a hardware co-processor that, starting from a pair of stereo images, computes the “disparity map” between them used to define corresponding points on the two images. The followed approach, based on Dynamic Programming, is that proposed in a recent paper and exploits the well known Needleman & Wunsch's string-alignment algorithm used in bioinformatics. The architecture, highly modular, was designed using Bluespec System Verilog development tool and is described in detail. Synthesis results are shown for several FPGA platforms and demonstrates that the processor can result sufficiently small to be embedded in a totally hardware stereo images processing chain. Performance obtained and reported at the end of the paper show that the processor can run fast enough to be employed in real time instances
Toward hardware implementation of DoG
No full textThis contribution presents STM’s latest advances in implementing selected parts of the TM into custom hardware devices, codenamed Stripe Based DoG (SBDoG) and proves to perform equivalently to Test Model 3.1. In detail, SBDoG includes the whole Difference of Gaussian (DoG) and Interest point (KP) detection logic as modeled by VLFeat 0.9.14.
The document reports the performances of the circuit with reference to the memory requirements of the structure
An Innovative Wireless Endoscopic Capsule With Spherical Shape
No full textThis paper aims to contribute to the advancement of the Wireless Capsule Endoscopy (WCE) field for ColoRectal Cancer (CRC) screening, by developing all electronic circuits to build an innovative wireless endoscopic capsule with a spherical shape, conceived to reduce the friction during its locomotion and thus improving patient’s acceptability. The proposed capsule embeds an image sensor with optics and Light Emitting Diodes (LEDs), a control unit with a telemetry module, an actuation system, a battery with a smart recharging circuit able to recharge in 20 minutes, a smart power-on circuit and a localization module. Everything is devised to fit in a small spherical shape with a diameter of 26 mm and a weight of 12.70 g. The authors present a description of the sub-modules involved in the capsule development, together with the firmware and hardware integration. In order to reduce the bandwidth for matching the specifications of the target commercial telemetry, the firmware interfacing of a custom encoder was performed, which is able to compress the incoming images with a negligible loss of information and occupying a number of Look Up-Tables (LUTs) less than 1780. As a preliminary work, a versatile Field Programmable Gate Arrays (FPGA) based demo-board system has been developed in order to test and optimize the functionalities and the performance of the single sub-modules and wireless vision chain system. This work allows to demonstrate the feasibility of a complex biomedical system, with severe constraints by highlighting the necessity to enhance the frame rate in the future
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