1,720,954 research outputs found
Device-Circuit Reliability Co-Design in High voltage and Power devices
No full textFor the last four decades, silicon CMOS technology has captured a significant share in IC, smart power IC, SoC, and the power device market. But there is aggressive research on other materials such as graphene & similar 2D materials and wideband gap materials. But, several aspects, including the fabrication process to improve device performance [7,9,12,13], understanding the device reliability physics [8,10,11], interconnection and packaging, need to be matured before these compound materials take the limelight. Besides these, a fab set-up for large scale production requires high NRE capital. On the other hand, Silicon had been through a great degree of maturity. Moreover, for intelligent power applications, Silicon has superior reliability. Therefore, Silicon is predicted to capture the power device market till the other materials gain perfection.
Besides the commercial market, the requirement for discrete and integrated power device technology within the strategic sector is enormous. Discrete power switching devices (often power MOS or IGBT switch) and power RF devices are used in numerous onboard power electronic and power RF applications. The first part of this work strives to bridge the device-circuit co-design gap that has severely limited predictive modelling of circuits for high power applications such as Radio Frequency Power Amplifiers (RF PAs) using high power devices LDMOSs and GaN HEMTs. A correlation between the device’s intrinsic parameters and PA performance is explored, and the iterative process aims to provide a high-performing circuit.
LDMOS is one of the prominent power devices which adopts CMOS processing and easy integration. The lateral double diffused MOSFET (LDMOS) is the predominant power device in implementing Power integrated circuits PICs because of its attractive electrical characteristics such as low on-resistance, high breakdown voltage, high input impedance and fast switching frequency. To obtain high breakdown voltage with low on-resistance for LDMOS, RESURF technology is used, in which the vertical p-n junction depletion layer between the n-type drift region and p-type epitaxial region and its interaction with lateral p-n junction depletion between the p-type channel and n-type drift region is optimised to reduce the surface electric field to obtain high breakdown voltage. A field plate (FP) on top of the gate and a drain field plate on top of the drift region is introduced to improve breakdown voltage further. These field plates help reduce feedback capacitance (Cgd) and increase the breakdown voltage FP LDMOS.
This work explores optimising the field plates for achieving breakdown characteristics above 900V without altering the on-resistance of the devices [2]. It covers major classical power devices from conventional design to non-conventional device designs. Conventional devices without field plates show 30% lower breakdown voltages than those with field plates. It can be concluded that field plates play a vital role in enhancing the breakdown characteristics of the device. Taking optimised design further, the field plates are introduced into non-conventional devices, where RESURF and SOI-based devices are explored. Along with the performance studies, the reliability of these structures is also explored. Regarding reliability, RESURF based devices show a higher tendency of deviation/degradation when stressed, up to 20% higher than the breakdown condition like that of the conventional devices without Fp. Further, the role of each field plate individually under the ESD condition is explored [3]. It was clearly understood that field plates at the source side play a significant role in distributing the junction electric field, while field relaxation at the drain side helps in improving the failure threshold. Gate and Source field plates improve the trigger voltage characteristics up to 54%, while drain field plate improves the failure threshold up to 60%.
Power semiconductor device industries are aggressively looking for system-on-chip (SOC) solutions for power amplifier (PA) circuits and are exploring different technologies, including gallium arsenide (GaAs), to more recent and intriguing gallium nitride (GaN) technologies, for power transistors with Radio Frequency (RF) applications. The advantage of silicon technology for RF applications lies mature fabrication process at low cost and their easy integration capability with the CMOS technology. Applications that require radio frequency power amplifiers such as broadcast, ISM (industrial, scientific, and medical), avionics, radar, wideband communications, telecom & satellite communications, RF heating applications, etc. Among them, the 50V RF LDMOS device is mainly used in wireless broadcast, ISM, and radar, which requires a higher breakdown voltage and power density. For 50V RF LDMOS with 0.35µm CMOS technology, the breakdown voltage must be higher than 100 V to guarantee a reliable operation. RESURF technology and the introduction of field plates have improved the breakdown voltage to 114V. Both DC and RF performance of various designs of FP RF LDMOS are evaluated, and results show that industry-leading performance is achieved [1]. Electrostatic Discharge (ESD) robustness was studied for the FP RF LDMOS designs as ESD has been identified as a source of damage to unprotected devices. Hot Carrier Injection (HCI) reliability was also investigated to address the complete reliability of these devices.
Though Silicon-based transistors have the advantage of mature technology, the requirement for high power and high-frequency devices demands transistors based on semiconductor materials with large breakdown voltage and high electron velocity. GaN is an attractive candidate for power amplifier applications because of several superior qualities in amplifier applications achieved due to its semiconductor properties. The wide bandgap in Gallium Nitride based transistors results in higher breakdown voltages because the ultimate breakdown field is the field required for band-to-band impact ionisation. Also, its high electron saturation velocities allow high-frequency operation. GaN can be used to fabricate high electron mobility transistors (HEMTs), which have high carrier concentration and higher electron mobility due to reduced ionised impurity scattering. A rigorous device-circuit co-design investigation of AlN/GaN HEMT to explore its feasibility for power amplifier operation at frequencies > 1THz. Both class A and class AB operations were invested. A novel device-circuit co-design methodology was adopted [4], which involves (i) device design optimisation using a well-calibrated TCAD setup, (ii) careful extraction of large-signal model cards with I-V, C-V & S-parameter matching, and finally (iii) source-load pull-based power amplifier design/exploration, for every device design investigated. For PA operation, both class A and class AB operations were invested while exploring PA gain, output power, efficiency at 1dB compression point, and linearity through dual-tone (IMD3) investigations. Besides, a complete range of device design parameters was investigated to explore the ultimate scalability limit and narrow down the device design window that can enable THz operation.
The last two decades have witnessed significant scaling in MOS technology from sub-micron to sub-nm level. To achieve devices with good performance at a small dimension, it was essential to explore new device architectures which could offer subthreshold swing (SS) values below 60 mV/dec. Several CMOS-like structures were designed, such as Fin-FETs, Nanowire Gate All Around (GAA) MOSFETs, Carbon nanotube FETs, Tunnel FETs, etc., which could lower the leakage current at small dimensions. Among these, TFET could achieve SS less than 60 mV/dec attributed to a fundamentally different mechanism for carrier injection. Hence, TFET is considered a future on the roadmap. A prediction of reliability is essential in choosing a device for a particular application. Therefore, it is necessary to understand the reliability of devices at the design stage itself. As technologies advance towards the deep submicron, the ESD (Electrostatic Discharge) protection design issues have become more critical. The second part of this work tries to understand the ESD robustness of a couple of novel Tunnel FET architectures.
A novel Fin-enabled vertical or area-scaled tunnelling FET is proposed for sub- 10-nm channel length operation. This device enables a smooth transition from FinFET technology to Fin-based vertical TFETs, while enjoying the benefits of FinFET architecture. To make this device commercial, it’s essential to understand the reliability performance of this device. This work explores the reliability physics of this device with detailed physical insight into the device’s operation and failure under ESD stress conditions [5]. The proposed device has a deep N+ implant underneath the P+ source, like adding a pocket between the source and gate for the ESD protection applications. Early avalanche assisted BTBT at the source-pocket junction, in addition to the drain-substrate junction, causes the device to turn on at lower voltages, lower self-heating resulting in improved failure current in the proposed device with less area overhead
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
koamabayili/VECTRON-author-checklist: VECTRON author checklist
No full textWe have done our best to complete the author checklist relating to the use of animals in the hut study. Note that the objective for the hut study was to evaluate the IRS treatment applications for residual efficacy against Anopheles mosquitoes, including the local An. coluzzii mosquito population. Cows were only used to attract mosquitoes into the huts and no tests were carried out directly on the cows. The author checklist is intended for use with studies where experiments are carried out on animals, which is why we have had such difficulty in completing this for the hut study, as many of the questions do not relate to how the cows were used
Author-wise bibliometric analysis based on entropy.
No full textAuthor-wise bibliometric analysis based on entropy.</p
Author Under Sail The Imagination of Jack London, 1893-1902
No full textIn Author Under Sail, Jay Williams offers the first complete literary biography of Jack London as a professional writer engaged in the labor of writing. It examines the authorial imagination in London's work, the use of imagination in both his fiction and nonfiction, and the ways he defined imagination in the creative process in his business dealings with his publishers, editors, and agents. In this first volume of a two-volume biography, Williams traverses the years 1893 to 1902, from London's "Story of a Typhoon" to The People of the Abyss. The Jack London who emerges in the pages of Author Under Sail is a writer whose partnership with publishers, most notably his productive alliance with George Brett of Macmillan, was one of the most formative in American literary history. London pioneered many author models during the heyday of realism and naturalism, blurring the boundaries of these popular genres by focusing on absorption and theatricality and the representation of the seen and unseen. London created an impassioned, sincere, and extremely personal realism unlike that of other American writers of the time. Author Under Sail is a literary tour de force that reveals the full range of London as writer, creative citizen, and entrepreneur at the same time it sheds light on the maverick side of machine-age literature.Intro -- Title Page -- Copyright Page -- Dedication -- Contents -- Acknowledgments -- Introduction -- 1. Spirit Truth -- 2. From Absorption to Theatricality and Back Again -- 3. "I Will Build a New Present" -- 4. Sons as Authors -- 5. Fathers as Publishers -- 6. The Daughter as Author -- 7. Lovers as Authors -- 8. At Sea with the Family -- 9. Yellow News, Yellow Stories -- 10. The Return Home -- Notes -- Bibliography -- Index -- About Jay WilliamsIn Author Under Sail, Jay Williams offers the first complete literary biography of Jack London as a professional writer engaged in the labor of writing. It examines the authorial imagination in London's work, the use of imagination in both his fiction and nonfiction, and the ways he defined imagination in the creative process in his business dealings with his publishers, editors, and agents. In this first volume of a two-volume biography, Williams traverses the years 1893 to 1902, from London's "Story of a Typhoon" to The People of the Abyss. The Jack London who emerges in the pages of Author Under Sail is a writer whose partnership with publishers, most notably his productive alliance with George Brett of Macmillan, was one of the most formative in American literary history. London pioneered many author models during the heyday of realism and naturalism, blurring the boundaries of these popular genres by focusing on absorption and theatricality and the representation of the seen and unseen. London created an impassioned, sincere, and extremely personal realism unlike that of other American writers of the time. Author Under Sail is a literary tour de force that reveals the full range of London as writer, creative citizen, and entrepreneur at the same time it sheds light on the maverick side of machine-age literature.Description based on publisher supplied metadata and other sources.Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, YYYY. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries
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