87,346 research outputs found
Substrate Engineering for Improved Transient Breakdown Voltage in SOI Lateral Power MOS
No full textAn innovative design concept for the silicon-oninsulator
(SOI) lateral power devices that can be applied to a wide
class of high-voltage applications, in particular those employing
resonant switching, is presented. A nonuniformly doped substrate
is used to improve the transient breakdown performance of the
lateral MOSTs. The simulation results show that the proposed
device exhibits a largely improved transient breakdown. That
is, for a time interval that ranges from 10 μs to 10 ms depending
on the silicon characteristics and temperature, the device
exhibits a blocking voltage that is almost double when compared
to the static blocking voltage. By using the novel concept presented
here, one can design a high-performance device with a high transient
breakdown, which is needed for most switching applications.
The device will benefit from a smaller substrate oxide thickness
designed for a lower static breakdown, which results in reduced
self-heating and allows full compatibility with the mainstream SOI
material
Circuital implementation of deep depletion SOI power devices
No full textCircuit implementations of deep depletion SOI devices are presented in this paper. Chosen switching topologies are a class E converter and a ZVS resonant step down converter. The newly proposed devices, named deep depletion devices, feature transient breakdown voltage higher than static breakdown voltage and are therefore ideally suited to those circuit implementations in which the maximum voltage applies to the power switch for a limited amount of time. Mixed-mode simulations of the circuits show that the proposed class of power devices can be profitably used in resonant power electronic circuits topologies
Substrate deep depletion: an innovative design concept to improve the voltage rating of SOI power devices
No full textThis paper, for the first time, proposes and experimentally demonstrates an innovative design concept for SOI power devices that exploits substrate deep depletion to considerably improve device voltage rating. This dynamic effect allows the design of a whole new generation of SOI power devices providing dramatically improved performances. Eligible applications are power conditioning circuits (flyback, resonant) in which the device sustains transient voltages higher than bus voltage. Numerical simulations explain the physics of the device. Experimental measurements on SOI power LDMOS using P substrate clearly demonstrate that the newly proposed "Deep depletion SOI device" presents 170V static breakdown voltage while sustains transient overvoltages up to 290V
Physics, limits and application of the newly proposed deep depletion SOI power devices
No full textThe behaviour of a deep depletion SOI LDMOS is thoroughly analyzed in this paper. Deep depletion of the substrate for a SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. The deep depletion is a dynamic effect that allows the design of a whole new generation of SOI power devices providing improved performances. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. In this paper numerical simulations are used to analyze the behaviour of the device together with the effect of temperature and substrate carrier generation time on the duration of the transient breakdown phase. Numerical results show that the newly proposed "deep depletion SOI device", a SOI power LDMOS using P substrate, exhibit 190V static breakdown voltage while sustains transient overvoltages up to 290V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed deep depletion SOI device is presented
The Effect of Charge Imbalance on Superjunction Power Devices: An Exact Analytical Solution
No full textCharge imbalance in the drift region of superjunction
(SJ) devices can significantly impair its breakdown voltage
(BV). An analytical solution for the electric field and the BV of
symmetrical SJ devices, which accounts for the effect of the charge imbalance, is proposed in this letter. The resulting equations are particularly simple and meaningful. They provide valuable insight into the effect of charge imbalance. A comparison of the analytical results with 2-D numerical simulations shows that the proposed model for symmetrical SJ devices can accurately predict the electric field distribution and the reduction in the BV due to charge imbalance in the drift layer
Analytical calculation of the breakdown voltage for balanced, symmetrical superjunction power devices
No full textThe superjunction concept allows the design of power semiconductor devices with improved performances compared to conventional sustaining layers. Due to the lack of accurate analytical models to characterize superjunction devices the design phase is still based on numerous and time consuming finite element simulations. In this paper a closed form analytical solution for the calculation of the breakdown voltage of a superjunction symmetric and charge balanced diode, is presented. The calculation of the breakdown voltage is based on the approximated solution of the ionization integral. The proposed solution is based on the Taylor expansion coupled with Newton Raphson algorithm
Modeling Turn-off Voltage rise in SOI LIGBT
No full textThe behavior of the drain voltage rise of the Lateral IGBT during inductive turn-off is studied in detail. Numerical simulations show that, if compared with the well known vertical IGBT, the Lateral IGBT presents a differences in the on-state stored charge and in the growth of the depleted region that result in a different drain voltage rise. In this paper a complete model for the voltage rise is devised through an accurate calculation of the equivalent output capacitance. The model is in excellent agreement with two-dimensional simulations. Further, the paper shows that previously proposed models, which targeted the vertical IGBT, are not adequate for the description of the turn-off voltage rise in the Lateral IGBT
ACCURATE PHYSICAL MODEL FOR THE LATERAL IGBT IN SILICON ON INSULATOR TECHNOLOGY
No full textMany vertical IGBT models are currently available. They have also been implemented in commercial simulators and describe device behavior both in steady-state and transient. However, no reliable device models have been proposed for the Lateral IGBT that is widely used in the field of smart power integrated circuits. In this paper a complete physical model for the Lateral IGBT fabricated in Silicon On Insulator technology is developed. The model is implemented in Pspice circuit simulator. Model results are compared against finite element device simulation. A comparison with the most common vertical IGBT Pspice model shows that vertical IGBT models are not able to correctly predict lateral IGBT behavior
Modeling Voltage Derivative During Inductive Turnoff in Thin SOI LIGBT
No full textThe lateral insulated gate bipolar transistor (IGBT)
behavior differs in many aspects from the well-studied vertical
IGBT. In this paper, the voltage derivative during inductive turnoff
for a silicon-on-insulator (SOI) lateral IGBT (LIGBT) is analyzed
in detail. A complete model which accounts for the voltage rise is
implemented through an accurate calculation of the equivalent
output capacitance. The model is in excellent agreement with
two-dimensional simulations and experimental results across a
wide range of conditions. Further, the paper shows that previously
proposed models, which targeted the vertical IGBT, are not adequate
for the description of the turnoff voltage rise in the LIGBT
On The Static Performance Of The RESURF LDMOSFETs For Power ICs
No full textThis paper introduces a technology-specific relation for the static performance of high voltage lateral diffused MOSFETs. A similar relation, only dependent on material properties, is available for vertical power devices. Here we show that the static performance of the lateral power devices is influenced by the REduced SURface Field effect. Hence a technology-specific relation between the breakdown voltage and the specific on-resistance is proposed. The relation is not only material dependent but also involves two technology-dependent parameters. The proposed technology-specific static relation is substantiated by 2D numerical simulations, 1D analytical models and experimental results taken from the literature
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