1,721,014 research outputs found
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A case for effective utilization of Direct Cache Access for big data workloads
Get PDFThe exploration of techniques to accelerate big data applicationshas been an active area of research. Although we have highly efficient computing cores and high-speed networks, the bottleneck in most big data applications has been the latency of data access. The foremost contributors to this latency are the network communication, storage systems, software stack and data transfer. Heterogeneous co-processors, FPGA accelerators, and flash based storage accelerators try to overcome this latency by offloading processing from the primary processor, but these cause additional overheads to an already costly data-center server and increase the total deployment cost. With an ever growing size of data, the need to exploit the available resources in the primary processor while achieving the best possible performance becomes increasingly necessary. A humble performance improvement of even 1\% goes a long way in a typical data center environment. Consequently, this work evaluates the effectiveness of Data Direct Input Output (DDIO) commonly known as Direct Cache Access (DCA) for I/O intensive big data workloads. We begin with a survey of various kinds and characteristics of big data workloads and then present the performance gain/loss due to DCA for I/O intensive workloads on Xeon E5 based servers. The big data applications are considerably different from the workloads traditionally used in architectural studies hence micro-benchmarks are used to emulate workloads which could gain/lose considerable performance when using direct cache access. Also, we present the performance of I/O intensive tasks from state of the art Cloudsuite benchmark suite. We finally make a case for the dynamic use of DCA in the processor for better performance of big data applications (change the percentage of cache available for DDIO to use or the cache levels DCA can access)
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Defusing the Tension between Security and Performance with Secure Microarchitectures
Get PDFThe pursuit of secure computation has always featured a tension between performance and security. Security mitigations often come with a high performance cost that can be manifested in serious environmental and economic impacts if they are employed, and in disastrous security and privacy breaches, if not. In the context of processor architectures, the security-performance tension is only growing as new attacks appear, each exploiting a crucial performance optimization, threatening to unwind decades of architectural gains. These hosts of attacks on microarchitectural optimizations painfully coincide with an era in which those performance optimizations are needed most – an era when Moore’s law is fading and Denard’s scaling is gone. In this dissertation we strive to defuse this security-performance tension by deepening our understanding of vulnerabilities in modern processors, providing efficient hardware support to enable security, and designing new high-performance secure architectures. We first show how performance optimizations can have devastating security implications by introducing a novel microarchitectural side-channel attack that targets Data Direct IO, a network packet processing optimization implemented by Intel (Chapter 1). Then, we propose Context-Sensitive Decoding (CSD), a framework that takes advantage of the instruction-to-micro-op translation that exists in most modern processors to provide security features (Chapter 2). Finally, we propose novel secure and fast architectures to mitigate vulnerabilities in two of the most crucial performance optimizations in modern processors: Speculative Execution (Chapter 3)and Simultaneous Multithreading (Chapter 4)
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Breaking the ISA Barrier in Modern Computing
Get PDFIn recent years, the computing landscape has witnessed a shift towards hardware specialization in response to the rapid growth and expansion of software, changing market risks, and fundamental technological limitations. However, the largest barrier to full exploitation of heterogeneity has by far been the difficulty of programming for them. There is a pressing need for systems that allow the exploitation of highly heterogeneous platforms without creating additional programmer burden. The goal of this dissertation is to empower the hardware/software interface, specifically the Instruction Set Architecture (ISA) and the runtime system, with diverse capabilities to enable the seamless adoption of heterogeneous hardware, without breaking the traditional models of programming.Existing heterogeneous designs either constrain CPU cores to feature a single ISA or allow multiple ISAs that assign distinct jobs to distinct cores, or at best statically partition work, resulting in a tight coupling of an application to the underlying ISA. This dissertation challenges the assumption that the single-ISA constraint is necessary, and further enables programs to cross a heretofore forbidden boundary -- the ISA. In particular, this dissertation describes a compiler and runtime strategy for swift and seamless process migration across diverse ISAs, and further showcases results from a massive core architecture optimization process that demonstrates the performance and energy efficiency benefits of multi-ISA heterogeneous architectures. In addition to its performance and energy efficiency benefits, this dissertation also explores and demonstrates the security potential of multi-ISA architectures to thwart several evasive variants of the notorious Return-Oriented Programming (ROP) attack. This dissertation further alleviates the complexity concerns of multi-vendor ISA heterogeneity by studying the effect of introducing composite-ISA heterogeneity into a microarchitecturally heterogeneous system, recreating and in many cases superseding the benefits that arise from multi-ISA heterogeneity, essentially with a single ISA
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Software Management of Memory Subsystem Contention on Multicore Systems
Get PDFThe multicore era has initiated a move to ubiquitous parallelization of software. In the process, cores have scaled out but the memory subsystem resources have not kept up. Memory subsystem contention within and between applications makes it challenging to extract performance scaling that matches the increase in the number of cores. This dissertation explores the diagnosis of memory subsystem contention, identifies associated performance and energy efficiency opportunities, and suggests techniques and optimizations to both precisely measure and reduce the contention. The dissertation begins by exploring contention within a single and between multiple, large-scale, distributed scientific applications and moves to exploring the impact of memory subsystem contention on graphics processing units, accelerators that are seeing increasing usage in both commercial data centers and scientific clusters. The findings of the studies demonstrate that memory subsystem contention is a serious impediment to achieving high performance and energy efficiency but also that relatively simple techniques that control job placement, resource sharing, tuning of parallelism, and algorithmic optimizations at the application level provide significant opportunities to improve performance and energy efficiency.The dissertation comprises four distinct works. (1) It begins by quantifying the performance and energy efficiency opportunities afforded by co-scheduling large-scale distributed scientific applications within a supercomputer. (2) From there, it studies the design of a prototype system for dynamically quantifying inter-application interference between co-located supercomputer jobs and uses those estimates to reform the accounting system to more fairly reflect end-user utility. (3) Next, it explores performance and energy scaling of analytic database workloads on graphics processors and finds that disabling whole compute units can reduce query execution time and reduce energy by throttling back the number of threads at any instant that contend for shared hardware resources. (4) The dissertation ends by describing the Horton table, a hash table that accelerates in-memory data-intensive computing by more efficiently using hardware cache and memory bandwidth
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Heterogeneity and Density Aware Design of Computing Systems
Get PDFThe number of programmable cores that are available in systems continues to increase with advances in device scaling, integration, and iterative improvements. Today, systems are not just integrating more cores, but also integrating a variety of different types of processing cores, resulting in dense heterogeneous systems. However, important questions remain about the design methodology for dense heterogeneous systems. This thesis seeks to address these questions. One typical methodology for heterogeneous system design is to comprise systems by using parts of homogeneous systems. Another commonly used technique to enable density is replication. However, these design methodologies are “heterogeneous system oblivious” and “density oblivious”. The components of the system are not aware or optimized for the heterogeneous system they would become a part of. Nor are they aware of the existence of other replicated components. This thesis shows that “heterogeneous system oblivious” and “density oblivious” design methodologies result in inefficient systems. This thesis proposes heterogeneity and density aware approaches to designing dense heterogeneous architectures
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Memory Safety for Today’s Languages and Architectures
Get PDFMemory safety vulnerabilities remain one of the most critical sources of exploitable security problems in today’s software. Despite the growing popularity of modern, memory-safe languages, much of today’s software remains written in C and C++, which are prone to these vulnerabilities; and rewriting all of this C and C++ code would be prohibitively expensive and time-consuming. At the same time, microarchitectural side-channel attacks threaten to violate memory safety in increasingly complex ways. But, new languages such as WebAssembly (Wasm), and new hardware features such as ARM MTE, give programmers new tools in the fight against memory safety vulnerabilities — and with clever use of these tools, we can obtain strong security guarantees for today’s software.In this dissertation, we present a variety of tools for improving memory safety for today’s C and C++ codebases, on today’s side-channel-prone microarchitectures. In the domain of finding memory-safety vulnerabilities, we first demonstrate how new microarchitectural features sometimes introduce new side-channel attacks (Chapter 1); then, we present program analysis tools which help keep programs secure from that class of side-channel attacks (Chapter 2) and from a newer and particularly relevant class of side-channel attacks, Spectre attacks (Chapter 3). In the remainder of the dissertation we focus on automatically preventing memory-safety vulnerabilities. We systematically compare and critique proposed software-based defenses against Spectre (Chapter 4); then we present one such defense, a tool which automatically and efficiently secures cryptographic programs against Spectre (Chapter 5). Starting with Chapter 6 we return to non-side-channel memory safety vulnerabilities, proposing an extension to Wasm which provides memory safety even inside its software sandbox; and finally, in Chapter 7 we present a compiler-based defense which works in conjunction with ARM MTE to automatically secure C and C++ programs from spatial memory safety vulnerabilities
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Software Techniques to Enhance Reliability of Emerging Compute and Memory Units
Get PDFSystem reliability is becoming a significant concern as technology continues to shrink. This is because of increasing variation in circuit characteristics seen in nanometer-scaled microsystems. These variations in semiconductor manufacturing manifest as increasing fault rates in devices, rising soft errors, and timing errors caused by accelerated aging in circuits. This dissertation seeks software-based techniques to detect, recover, and prevent such errors in compute and memory components.Software-based error detection and recovery techniques suffer from high-performance penalty to the overall system. This thesis presents methods that minimize the performance overhead of software-based error mitigation. In particular, this work proposes two techniques for effective software-based error detection in compute units: fingerprinting and cross-laneinstruction. Fingerprinting combines multiple error detection events into one event by hashing, and cross-lane instruction enables error checking via low latency register-level communication. Furthermore, to reduce the performance overhead of software-based recovery, this thesis explores Application-Specific Approximate Recovery (ASAR). ASAR trades-off output quality to reduce the performance penalty of software-based recovery.Variation affects not just compute but memory components, as well. For memory units, we focus on methods for proactive error prevention. Given the diversity of memory components in use, we focus on emerging Heterogeneous Memory Architectures (HMAs). An HMA consists of multiple memory modules with different performance and reliability characteristics. These differences can be caused by different types of memory modules, different error correcting codes, and effects due to aging. This thesis focuses on methods to place and move data items among memory modules in an HMA system with the goal of reducing the likelihood of encountering an error. Specifically, this work describes two novel data placement techniques: age-aware and vulnerability-aware data placement. The age-aware technique monitors the accumulation of faults in different memory modules as they age, while the vulnerability-aware technique estimates the vulnerability of data in memory to soft errors. The results presented in this work enable practical use of software-based error mitigation solutions for current and future hardware
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Achieving Accurate Predictions of Future Events Under Hardware Heterogeneity
Get PDFHeterogeneous hardware is becoming increasingly available in modern hardware, while research breakthroughs enforce the expectation that heterogeneity will keep increasing in the future. Significant gains can be achieved via appropriate utilization of heterogeneity, in terms of performance and power consumption, however, poor utilization can have a detrimental effect. Intelligent scheduling and resource management is a crucial challenge we need to overcome in order to harvest the full potential of heterogeneous hardware. As systems become larger and include greater levels of hardware diversity, the importance of intelligent scheduling and resource management is further accentuated.This dissertation presents techniques that aid the process of scheduling and resource management in the presence of heterogeneous hardware, via accurately predicting upcoming runtime events. With a proactive and accurate view of the near future, schedulers can utilize the underlying hardware more efficiently, and fully take advantage of the available benefits.By adapting a majority element heuristic, this dissertation significantly improves the accuracy of predicting memory addresses about to be accessed, while reducing prediction-related costs by a factor of ten thousand compared to previously proposed predictive approaches. Coupled with novel microarchitectural modifications, accurate address predictions are shown to improve the performance of heterogeneous memory architectures.Machine learning-based performance predictors are further presented, capable of predicting a program's performance when executed on a given general-purpose core. Trained to model the subtleties of the interaction between hardware and software, these predictors are capable of generating highly accurate predictions even for cores with varied Instruction Set Architectures. Utilizing these performance predictions for job scheduling, is shown to improve overall system performance. The trained predictors are further examined and interpreted in order to visualize the correlations between features picked up and amplified during training.Finally, this dissertation demonstrates that scheduling algorithms cannot guarantee deriving an optimal schedule during realistic execution scenarios due to the underlying hardware heterogeneity, the wide range of runtime requirements of software, as well as prediction error from performance predictors. In response, deep neural networks are trained to select one scheduling approach from a list of options with varied overheads and correctness guarantees. The scheduling approach chosen, is the one which will most likely return the highest-performance schedule with the lowest overhead, given a particular instance of the job-to-core assignment problem
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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