76 research outputs found
Clock multiplication techniques for high-speed I/Os
No full textGeneration of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored.
First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.
Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB.
Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01The student, Romesh Kumar Nandwana, accepted the attached license on 2017-04-17 at 15:09.The student, Romesh Kumar Nandwana, submitted this Dissertation for approval on 2017-04-17 at 15:42.This Dissertation was approved for publication on 2017-04-19 at 08:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #10816 on 2017-08-10 at 15:05:48Made available in DSpace on 2017-08-10T20:32:59Z (GMT). No. of bitstreams: 3
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LICENSE.txt: 4218 bytes, checksum: a246f466819d5f63b537a54ce4202fa9 (MD5)
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Previous issue date: 2017-04-19Embargo set by: Colleen Fallaw for item 102771
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Pi from Probability Approach
No full textIn this paper I introduced a new Probability mass function (Pmf) that is named as Pavan’s Pmf then used first and second raw moments of that distribution and De Moivre-Laplace theorem for large n later equated probability functions of binomial and normal distribution at model value to derive the formula for Pi
Event-driven simulation of mixed-signal systems
No full textSubmission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2022-05-01This thesis presents a method of performing fast and accurate simulation for mixed-signal systems. The first section introduces traditional simulation methods for mixed-signal systems and their drawbacks. The second section shows a new way to perform such simulation in a fast and accurate way, using the event-driven simulation method. For illustrative purposes, a type-2 charge-pump phase-locked loop is implemented. The third section is an extension to the second one: nonlinear effect is also included in the system.The student, Yongxin Li, accepted the attached license on 2020-04-09 at 09:52.The student, Yongxin Li, submitted this Thesis for approval on 2020-04-09 at 10:02.This Thesis was approved for publication on 2020-04-10 at 10:32.DSpace SAF Submission Ingestion Package generated from Vireo submission #14947 on 2020-08-25 at 17:27:14Made available in DSpace on 2020-08-26T23:51:27Z (GMT). No. of bitstreams: 2
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At the Crossroads: Multidiscipline Integration and Coordination in an EPC Contract: A Resurgence of Challenges and Strategic Improvement Opportunities
No full textMaster's thesis in Industrial Asset ManagementOver the years, the faculty of Project management contributed excellent methodologies through a set of constituted guidelines that are applicable for smooth execution of projects in every industry. They are broadly based on initiating, planning, organizing, executing, and monitoring & controlling the process groups as a single entity. The implementation of project management methodologies is carried out through project management knowledge in specialized areas such as integration, scope, time, cost, quality, human resource, communications and risk. Projects are governed by factors that have major influence in directing the success or failures. Broadly cost, time & quality have been identified as key important success factors for projects. However, the factors are also governed by the complexity of projects and risk involved in project execution.
Over the decades the EPC contractors are trying to find solutions to cope up to the complexities colligated with significant risks in project execution. Extensive research is done by every contractor with an objective to integrate schedule and time management functions in an EPC project. Many scholars and researchers used different methodologies such as utility theory, scheduling milestones, cost milestones, performance index, cost accounting etc.
However, the focus has been primarily on the construction phase of the project and most often ignores the fact that success delivery of a project is a synchronous and integrated effort of all the disciplines involved in project execution.
This research is carried out to identify the critical success factors in EPC projects and establish the essential factors requisite for efficient execution. In a quest to define a framework that essentially facilitates identifying the critical success factors and their key influencing factors, a systematic investigation of established facts were used. The journey in search of knowledge through previously established researches and scholarly work culminated into the design and development of a framework methodology congenial to the current research environment. Collaboration with the research unit specialist groups and individuals helped to develop a survey questionnaire. The required data was acquired from selected participants of the EPC contractor organization that is specialized in offering EPC services in the oil & gas industry. The data was collected based on convenience statistical sampling technique. Acquired data was analyzed through univariate, bivariate, multivariate statistical techniques and identified the critical factors that require attention of the management of the organization under research. The findings indicated concurrence of established project success factors i.e. scope, time and cost with critical success factors identified and defined in the research. The results of analysis identified factors that are significantly affecting the efficiency of multidiscipline integration and co-ordination.
The research established that an integrated control system is necessary to the management as a tool that investigates and provides answers from the project stakeholders. Such a system provides the reflection of the factors that are directly or indirectly impacting the cost, schedule and quality constraints of a project.
Research Faculty Supervisor: Professor. Jayantha.P. Liyanage, Ph.D,
Professor & Chair, Centre for Industrial Asset Management (CIAM),
Faculty of Science & Technology, University of Stavanger
Research External Supervisors: Nils Erik Olsen and Eivind Eliassen
Researcher and Author: Pavan Kumar Akella
M.Sc Student, Faculty of Science & Technology,
University of Stavange
RC relaxational oscillator with high supply rejection
No full textA low power RC relaxation oscillator with very low voltage and temperature sensitivities is presented. Supply sensitivity is reduced by using a self-regulation loop that biases the oscillator near its zero-voltage coefficient point. Fabricated in a 65nm CMOS process, the prototype 1.5MHz oscillator consumes 6μW from 1V supply and achieves better than ±50ppm/ ̊C and ±1500ppm/V temperature and voltage sensitivities, respectively.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-05-01The student, Tianyu Wang, accepted the attached license on 2018-04-25 at 16:33.The student, Tianyu Wang, submitted this Thesis for approval on 2018-04-25 at 16:37.This Thesis was approved for publication on 2018-04-26 at 08:25.DSpace SAF Submission Ingestion Package generated from Vireo submission #12497 on 2018-08-31 at 17:30:30Made available in DSpace on 2018-09-04T20:47:31Z (GMT). No. of bitstreams: 2
WANG-THESIS-2018.pdf: 1064625 bytes, checksum: 8253049aced9902739dce149c03027dd (MD5)
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Previous issue date: 2018-04-26Embargo set by: Seth Robbins for item 107462
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Clock distribution network techniques
No full textClock distribution networks are essential to synchronous systems. The design of these networks affects the system performance dramatically and sometimes determines whether the chip can function properly or not. This thesis first describes in detail how a synchronous system works. Based on the design metrics such as the clock skew requirement and power requirement, different clock distribution network topologies are then presented, including the popular H tree, grid and serpentine structures. Finally, commonly used techniques for improving clock skew, jitter and power are discussed and conclusions are offered.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-08-01The student, Shuang Chen, accepted the attached license on 2020-06-26 at 16:40.The student, Shuang Chen, submitted this Thesis for approval on 2020-06-26 at 16:50.This Thesis was approved for publication on 2020-06-29 at 15:08.DSpace SAF Submission Ingestion Package generated from Vireo submission #15473 on 2020-10-02 at 15:49:41Made available in DSpace on 2020-10-07T22:48:09Z (GMT). No. of bitstreams: 2
CHEN-THESIS-2020.pdf: 770570 bytes, checksum: 068cedd8d6fc58470b4144a4e4835913 (MD5)
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Energy-efficient wireline transceivers
No full textPower-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50.The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42.This Dissertation was approved for publication on 2016-09-30 at 13:20.DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3
SHU-DISSERTATION-2016.pdf: 13625828 bytes, checksum: 6f7a554d7374c812e5874362c8a3664a (MD5)
LICENSE.txt: 4209 bytes, checksum: 9364f41c0fe9c8f540827190943f3d0f (MD5)
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Previous issue date: 2016-09-30Embargo set by: Seth Robbins for item 98665
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Analysis of inductance-capacitance voltage-controlled oscillators
No full textThis thesis focuses on analysis of inductance-capacitance voltage-controlled oscillators (LC VCOs), specifically, double switch cross-coupled oscillators. Fundamentals on LC VCOs, like oscillation conditions, classical LC VCO architectures, inductor and capacitor choices, and phase noise calculations are described. A detailed analysis of the phase noise and oscillation amplitude of double switch cross-coupled oscillators follows. Tail imperfections of cross-coupled oscillators are also discussed, and a brief design guideline is introduced.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2021-05-01The student, Yi Zhu, accepted the attached license on 2019-04-16 at 09:55.The student, Yi Zhu, submitted this Thesis for approval on 2019-04-16 at 10:09.This Thesis was approved for publication on 2019-04-16 at 15:08.DSpace SAF Submission Ingestion Package generated from Vireo submission #13665 on 2019-08-22 at 15:06:41Made available in DSpace on 2019-08-23T20:35:56Z (GMT). No. of bitstreams: 2
ZHU-THESIS-2019.pdf: 827454 bytes, checksum: eba59d2a1593bc11d8622516002836ea (MD5)
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Previous issue date: 2019-04-16Embargo set by: Seth Robbins for item 112155
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100 MHZ temperature compensated RC oscillator
No full textSubmission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2023-12-01The student, Ruhao Xia, accepted the attached license on 2021-12-08 at 19:10.The student, Ruhao Xia, submitted this Thesis for approval on 2021-12-08 at 19:17.This Thesis was approved for publication on 2021-12-09 at 08:43.DSpace SAF Submission Ingestion Package generated from Vireo submission #17410 on 2022-04-29 at 16:10:40Made available in DSpace on 2022-04-29T21:58:40Z (GMT). No. of bitstreams: 2
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Previous issue date: 2021-12-09Embargo set by: Seth Robbins for item 123473
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Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemAuthor requested closed access (OA after 2yrs) in Vireo ETD systemLimitedThis thesis presents a temperature-compensated RC oscillator architecture. The first section introduces the background and summarizes the previous work of temperature-compensated RC oscillator design. The second section shows the proposed architecture and explains the operation of proposed oscillator. The third section analyzes the design considerations including resistor choice and effects of approximation to simplify the model. The forth section will show the detailed circuit implementation followed by the fifth section showing the corresponding simulation results. The last section will be the conclusion for this thesis
A temperature-compensated RC oscillator using temperature sensor
No full textHighly stable clock reference is critical to many applications, including communication, timing, frequency synthesis, and synchronization. This thesis introduces a practice of utilizing a temperature sensor to compensate for an RC oscillator based on FLL (frequency-locked loop), on the same die of the temperature sensor, with the assistance of a frequency counter and a computer. The TCO (temperature-compensated oscillator) and the temperature sensor are presented by Khashaba et al. (2020). The additional digital circuitry for compensation can be further integrated on-chip. The achieved output frequency at 37.5 MHz varies by 875 ppm (parts per million) across the whole temperature range from -30 C to +80 C.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-05-01The student, Ducheng Qian, accepted the attached license on 2020-05-06 at 01:11.The student, Ducheng Qian, submitted this Thesis for approval on 2020-05-06 at 01:23.This Thesis was approved for publication on 2020-05-11 at 06:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #15239 on 2020-08-25 at 17:43:18Made available in DSpace on 2020-08-27T00:51:26Z (GMT). No. of bitstreams: 3
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A temperature compensated RC oscillator using temperature sensor.zip: 1697339 bytes, checksum: ef2d4063fea40b73ba4262ff1c2739f9 (MD5)
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Previous issue date: 2020-05-11Embargo set by: Seth Robbins for item 115934
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