2,275 research outputs found
Won’t on-chip clock calibration guarantee performance boost and product quality?
No full textIn today’s high performance (multi-GHz) microprocessors’ design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We will show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations’ compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in Defect Level. Similarly, we will show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors’ design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem will be discussed
New Design For Testability Approach for Clock Fault Testing
No full textWe propose a new design for testability approach for testing clock faults of next generation high performance microprocessors. In fact, it has been shown that conventional manufacturing test is unable to guarantee their detection, although they could compromise the effectiveness of delay fault testing, as well as the microprocessor correct operation in the field. These conditions
will of course worsen with technology scaling, due to the expected increase in fault likelihood, included clock faults. To deal with these
problems we propose a design for testability approach that, by means of simple modifications to conventional clock buffers, allows
clock fault detection through any conventional manufacturing test approach. This is achieved at the cost of very low increase in area
and power consumption of clock buffers, and with no additional test cost or impact on the microprocessor performance and in-field
operation. We then introduce a possible further modification to clock buffers that, at additional limited costs in terms of area and power consumption, allows their calibration after fabrication in order to compensate for parameter variations possibly occurring during manufacturing, thus minimizing the likelihood of either false test fails, or test misses. As an example, we show the application of our approach to the clock distribution network of the Pentium14 microprocessor (Other names and brands may be claimed as property of others). However, it can be applied to the clock distribution of any high performance ASIC, or microprocessor
Novel Compensation Scheme for Local Clocks of High Performance Microprocessors
No full textClock compensation for process variations and
manufacturing defects is a key strategy to achieve high
performance of processors and high end ASIC. However,
with the increase in process variations and defect
densities, clock compensation is becoming increasingly
challenging. A clock distribution system also consumes
over 30% of the overall chip level power, so every little bit
counts, including compensation schemes. In this paper we
propose a new scheme for the compensation of
undesirable skews and duty-cycle variations of local
clocks of high performance microprocessors and high end
ASICs. Our scheme performs compensation continuously,
during the microprocessor operation, thus allowing also
compensation to clock jitters due to environmental
influences during operation. Compared to alternate
solutions for local clock compensation, our scheme
features lower power consumption, smaller compensation
error, and a lower or comparable area overhead, while
allowing compensation to be accomplished within the
same clock cycle of skew or duty-cycle variation
Novel Approach to Clock Fault Testing for High Performance Microprocessors
No full textIn this paper we present a novel approach for testing
clock faults for high performance microprocessors.
Although such faults have been shown to be likely and
could compromise delay fault testing, conventional
manufacturing test methodology is unable to guarantee
their detection. In this paper, we propose a modification
to the conventional clock buffers allowing standard
manufacturing test to detect the faults. This is achieved
at the cost of a small increase in area and power
consumption of the clock buffers, but with no additional
test cost or impact on the microprocessor performance
and in-field operation. Our approach can be applied to
the clock system of any high performance chip or
microprocessor
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing
No full textBased on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most
likely to affect signals of the clock distribution network. Their
probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations.
We have found that, contrary to common assumptions, only a small
percentage of such faults result in catastrophic failures easily
detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself
Low-cost on-chip clock jitter measurement scheme
No full textIn this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution
On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter
No full textWe present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despite the possible presence of significant process parameter variations
Attenuation performance of a semi-active Helmholtz resonator in a grazing flow duct
No full textAuthor name used in this publication: Mak, Cheuk Ming2012-2013 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishedC
Penerapan Pemasaran Digital Pada UMKM Canai Mak Fajar Di Bengkalis
No full textThe aim of conducting digital marketing at Canai Mak Fajar MSMEs is to find out the marketing mix such as: product, price, place and promotions that have been carried out at Canai Mak Fajar MSMEs, to implement digital marketing as a sales strategy, and to find out the obstacles and solutions faced during the marketing process. This project implementation method consists of four stages, namely project preparation, project implementation, project completion, and project reporting. Thus, the final result of this product is to apply digital marketing in the development of Canai Mak Fajar MSMEs in Bengkalis. The digital marketing process is divided into several stages: the process of making roti canai, the process of creating social media accounts, and marketing products on social media. The obstacle faced when implementing digital marketing is that the author has to think of interesting content ideas every day that can attract consumers' buying interest so that Canai Mak Fajar products are better known to many people in Bengkalis City as well as in remote areas of Bengkalis. The solution taken by the author must be extra in looking for references for interesting and up-to-date content ideas so that consumers are interested in buying canai at UMKM Canai Mak Fajar. It can be concluded that the implementation of digital marketing that has been carried out has had a positive impact
Can clock faults be detected through functional test?
No full textWe analyze the probability to detect clock faults indirectly through conventional functional testing by considering realistic datapaths derived from ISCAS'85 benchmarks. We show that, even optimistically assuming that we are able to test all short and long paths for min and max delay violations, the detection of clock faults can not be guaranteed, thus mandating new, specific testing approaches for clock faults, otherwise possibly compromising the system correct operation in the field, with dramatic consequences on product quality and defect level
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