1,037 research outputs found
Clock calibration faults and their impact on quality of high performance microprocessors
No full textIn this paper we analyze the fault effects of some clock calibration features which are common to today's high performance microprocessors. We show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g. scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that very deep sub-micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignore
Won’t on-chip clock calibration guarantee performance boost and product quality?
No full textIn today’s high performance (multi-GHz) microprocessors’ design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We will show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations’ compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in Defect Level. Similarly, we will show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors’ design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem will be discussed
The other side of the timing equation: a result of clock faults
No full textWe analyze the impact of clock faults on product quality and operation in the field. We show that clock faults could: i) give rise to min delay violations; ii) compromise the effectiveness of delay fault testing in screening out possible delay faults; iii) be missed by current functional testing (in addition to possibly be missed by structural testing, as proven by Metra et al. (2004). Therefore, new testing/DFT approaches are needed to avoid the dramatic impact of clock faults on product quality and operation in the field. Various possible approaches are discussed
Clock faults induced min and max delay violations
No full textIn this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations
Low-cost on-chip clock jitter measurement scheme
No full textIn this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution
Implications of Clock Distribution Faults and Issues with Screening Them During Manufacturing Testing
No full textBased on real process data of a reference microprocessor, fault models are derived for the manufacturing defects most
likely to affect signals of the clock distribution network. Their
probability is estimated with Inductive Fault Analysis performed on the actual layout of the reference microprocessor. The effects of the most likely faults have been evaluated by electrical level simulations.
We have found that, contrary to common assumptions, only a small
percentage of such faults result in catastrophic failures easily
detected during manufacturing testing. On the contrary, the majority of such faults lead to local failures not likely to be detected during manufacturing testing, despite their possibly compromising the microprocessor operation and reliability. In particular, we have found that the clock faults can be detected during manufacturing testing in only 12 percent of cases. Even more surprisingly, we have also found that, in 10 percent of cases, the undetected clock faults also invalidate the testing procedure itself
Attenuation performance of a semi-active Helmholtz resonator in a grazing flow duct
No full textAuthor name used in this publication: Mak, Cheuk Ming2012-2013 > Academic research: refereed > Publication in refereed journalVersion of RecordPublishedC
Penerapan Pemasaran Digital Pada UMKM Canai Mak Fajar Di Bengkalis
No full textThe aim of conducting digital marketing at Canai Mak Fajar MSMEs is to find out the marketing mix such as: product, price, place and promotions that have been carried out at Canai Mak Fajar MSMEs, to implement digital marketing as a sales strategy, and to find out the obstacles and solutions faced during the marketing process. This project implementation method consists of four stages, namely project preparation, project implementation, project completion, and project reporting. Thus, the final result of this product is to apply digital marketing in the development of Canai Mak Fajar MSMEs in Bengkalis. The digital marketing process is divided into several stages: the process of making roti canai, the process of creating social media accounts, and marketing products on social media. The obstacle faced when implementing digital marketing is that the author has to think of interesting content ideas every day that can attract consumers' buying interest so that Canai Mak Fajar products are better known to many people in Bengkalis City as well as in remote areas of Bengkalis. The solution taken by the author must be extra in looking for references for interesting and up-to-date content ideas so that consumers are interested in buying canai at UMKM Canai Mak Fajar. It can be concluded that the implementation of digital marketing that has been carried out has had a positive impact
Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors
No full textIn this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs
Review of "Moyu Yanjiu A study of Mak"
No full textMoyu Yanjiu is a linguistic and ethnographic description of the Mak language (a Kam-Sui language in the Kadai phylum) and its speakers, who live in the Lingnan Buyi-Miao Autonomous Zone of Guizhou, China. It actually draws grammatical examples largely from (Ai-)Cham, which until now has been described as a separate language close to Mak, but which the author argues is merely a sister dialect of the same language. Following is a summary of the contents of the book, completed with an evaluation of its contents.Published versio
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