1,720,981 research outputs found
A New Surface Potential and Physics Based Compact Model for a-IGZO TFTs at Multinanoscale for High Retention and Low-Power DRAM Application
No full textDevice modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression
Full text linkAmorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (V(T)), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µ(FE)) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), V(T) roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (V(O)) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as V(T), SCE, SS, and µ(FE), of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of V(O) and O in two-step oxygen anneal process
Open volume defects in ultra-thin TiO2 layers embedded in VMCO-like samples studied with positron annihilation spectroscopy
Full text linkPositron annihilation signals from VMCO-like samples grown by atomic layer deposition at different temperatures are utilized for the characterization of differences in open volume defects in TiN/TiO2/a-Si heterostructures. Doppler and coincidence Doppler mode of positron annihilation spectroscopy combined with a monoenergetic positron beam were used for this study. Differences observed in the Doppler parameters indicate differences in the positron trapping states of the TiO2 epilayers grown at different temperatures. Furthermore, the coincidence-Doppler results show that these differences cannot be due to intermixing of the TiO2 and a-Si layers and formation of thin SiO2 layers at the interface during the growth process. The results indicate that the amount of open volume defects in the TiO2 layer of the VMCO-structure seems to increase with an increase in the growth temperature.Peer reviewe
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays
No full textThe authors would like to thank the ECSEL joint undertaking project ANDANTE supported by European Union's Horizon 2020 Framework Program, Grant No. 876925. This work is also supported by the imec Industrial Affiliation Program. We acknowledge the useful discussions with Andrea Fantini and the measurement support from amsimec
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays
No full textExtensive reliability investigation of a-VMCO nonfilamentary RRAM: relaxation, retention and key differences to filamentary switching
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