1,720,989 research outputs found
Single-poly floating-gate memory cell options for analog neural networks
Full text linkIn this paper, we explore the use of a 180 nm CMOS single-poly technology platform for realizing analog Deep Neural Network integrated circuits. The analysis focuses on analog vector–matrix multiplier architectures, one of the main building blocks of a neural network, implementing in-memory computation using Floating-Gate multi-level non-volatile memories. We present two memory options, suited either for current-mode or for time-domain vector–matrix multiplier implementations, with low–voltage charge-injection program and erase operations. The effects of a limited accuracy are also investigated through system-level simulations, by accounting for the temperature dependence of the stored weights and the corresponding impact on the network error rate
A 0.05 mm2, 350 mV, 14 nW fully-integrated temperature sensor in 180-nm CMOS
Full text linkIn this brief, we present a fully-integrated ring-oscillator based CMOS temperature sensor for Internet-of-Things. Our design relies on a low-complexity PMOS-based sensing circuit to convert temperature into two sub-threshold biasing currents. These are then used to define two oscillation frequencies, whose ratio increases linearly with the temperature. Change in the frequency ratio is finally translated into a digital output code. The proposed sensor was fabricated in 180-nm CMOS technology. When powered at 350 mV, it can achieve an energy/conversion of 0.46 nJ in a conversion time of 33 ms. Moreover, it exhibits a measurement resolution of 0.27 °C and a resolution figure-of-merit as low as 0.034 nJ °C2,
The case for hybrid analog neuromorphic chips based on silicon and 2D materials
No full textWe discuss two closely related technologies for the fabrication of analog neuromorphic circuits, one based on a standard silicon CMOS process and a second one based on heterostructures of two-dimensional materials (2DMs). We analyze the relative advantages and disadvantages of such solutions and the case for a hybrid technology, that can leverage the advantages of both. We show that floating-gate FETs - both in silicon and 2DMs - are very promising as analog non-volatile memories (NVMs) enabling good analog computing precision, which is a distinct advantage with respect to other proposed NVMs. We show that the challenge of equipping devices at the edge of the cloud with cognitive capabilities can be addressed using large analog blocks in machine learning chips and innovations in architectures, circuits, and technology
Load Modulation Feedback in Adaptive Matching Networks for Low-Coupling Wireless Power Transfer Systems
Full text linkThis paper explores the use of load modulation feedback (LMF) in adaptive matching networks (MN) for low-coupling inductive wireless power transfer systems, with an emphasis on its use in implantable medical devices. After deriving the handy expressions of link efficiency and modulation depth in the case of LMF in the case of loose coupling, a brief overview of the most common capacitive resonance networks is presented. In particular, the MN employing two capacitors in Series–Parallel and in Parallel–Series configurations allow adaptivity with a wide range of load
conditions. Then, the authors describe an effective design procedure of an adaptive matching network with LMF for an inductive wireless power transfer system, exploring the trade-off between power efficiency and modulation depth. Analytical and electrical simulations show that the proposed simple modulation strategy can successfully achieve high power transfer efficiency while maintaining steady back telemetry under varying loading conditions
High-Temperature 13-Bit Delta-Sigma ADC in Standard SOI CMOS Operating Up to 260°C
No full textIn this paper, we present a 1.8-V 2nd-order DeltaSigma ADC for high-temperature operation, featuring 13 bits of ENOB and 150 Hz of bandwidth at 260°C. The chip is designed with a 180-nm SOI CMOS process, pushed well beyond its temperature qualification limit of 175°C through ad-hoc design techniques. The junction and channel leakage currents dependence on the temperature are carefully assessed and their negative effects on circuit performance are compensated using clock boosting and dummy transistor techniques. The converter, which has been experimentally characterized up to 270°C, achieves excellent performance up to 260°C: a Signal-to-Noise Ratio of 86 dB and a Signal-to-Noise-and-Distortion Ratio of 82 dB have been measured within a bandwidth of 150 Hz and for an oversampling ratio of 512
Ultralow voltage finFET-versus TFET-based STT-MRAM cells for iot applications
Full text linkSpin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET-and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%
A 0.6V–1.8V Compact Temperature Sensor with 0.24 °C Resolution, ±1.4 °C Inaccuracy and 1.06 nJ per Conversion
No full textThis paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit to convert the local temperature into two biasing currents. These are then used to define two oscillation frequencies, whose ratio is proportional to absolute-temperature. Finally, the sensor back-end translates such frequency ratio into the digital temperature code. Thanks to its low-complexity architecture, the proposed design achieves a very compact footprint along with low-power consumption and high accuracy in a wide temperature range. Moreover, thanks to a simple embedded line regulation mechanism, our sensor supports voltage-scalability. The design was prototyped in a 180nm CMOS technology with a 0 °C – 100 °C temperature detection range, a very wide supply voltage operating range from 0.6V up to 1.8V and very small silicon area occupation of just 0.021mm2. Experimental measurements performed on 20 test chips have shown very competitive figures of merit, including a resolution of 0.24 °C, an inaccuracy of ±1.4 °C, a sampling rate of about 1.5 kHz and an energy per conversion of 1.06 nJ at 30 °C
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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