35 research outputs found
Configurable version management hardware transactional memory for embedded multiprocessor field-programmable gate array
Get PDFMultiprocessor platforms have been introduced to solve the performance limitation of uni-processor platform. However, programming on a shared memory multiprocessor platform in an efficient way is difficult. The inefficiency of lock based synchronization limits the performance of the parallel programs. Transactional memory (TM) provides a promising method in creating an abstraction layer for programmers to maximize hardware capacity of multiprocessor platform. Hardware TM (HTM) is faster compared to software TM although the performance of hardware transactional memory (HTM) is application-specific. Previous HTM implementations for embedded system were built on fixed version management which results in significant performance loss when transaction behaviour changes. In this thesis, a configurable version management HTM is proposed. The proposed version management is able to be configured to eager version management for low contention applications since it allows fast commit, or lazy version management that is suitable for applications with high contention since it can abort fast. In this work, an analytical model of the proposed hardware transactional processing time for different version management has been developed. With the analytical model, the bounds of the worst case and best case processing time can be estimated for a particular transaction size. The switching point of the performance between eager and lazy version management can also be estimated. The HTM has been prototyped and analyzed on Altera Cyclone IV platform. Based on our experiments, lazy version management is able to obtain up to 12.82% speed-up while eager version management obtains up to 37.84% speedup on different memory request distributions for transaction sizes of 4, 8 and 16. The proposed HTM can be configured to obtain a shorter processing time for different types of applications compared to fixed version management
Interactive graphical user interface for incentive spirometer
Get PDFIncremental Decremental Support Vector Machine (IDSVM) is one of the widely used incremental learning algorithms known for its high accuracy for data stream analytics and high computational complexity. One of the biggest problems of IDSVM is that the model scales with the input data set size that directly correlates with the computational and memory resources. In order to deploy IDSVM in an embedded system with limited memory, a moving windowarchitecture is needed to limit the kernel sizes. However, this also increases the overall complexity of the algorithm since each data instance needs to be unlearned when exiting the window. This thesis proposes an Interleaved IDSVM (IIDSVM) algorithm that performs incremental and decremental learning concurrently. The interleaved method can reduce the overall kernel size and consume less memory. This thesis also proposes a reduced-division IIDSVMalgorithm that replaces the more complex division operations with simpler inverse multiplications. Certain IIDSVM tasks can be simplified by replacing most of the complex divisions with inverse multiplication that can achieve a similar outcome since only a single sample variation value is used to update the weights.Finally, a Radial Basis Function (RBF) kernel, which is a widely used kernel in SVM, is proposed to be implemented as a hardware accelerator to speed up the computation time of the IIDSVM. Based on our experiments, the proposed IIDSVM achieved a speedup of 2.5 - 4.2× on computation time while producing similar accuracy as IDSVM and LIBSVM. Furthermore, the reduced-division IIDSVM can improve computation time up to 1.4× on a Nios II embedded platform for certain data sets. The RBF kernel’s hardware implementation is analyzed on the Stratix V Field Programmable Gate Array (FPGA) platform. It can perform up to four orders of magnitude faster than the software implementation on the Nios II embedded processor for data sets with 8, 12, and 16 feature sizes. Besides that, the proposed architecture RBF kernel can maintain a maximum operating frequency of approximately 200Mhz for feature sizes 8, 12, and 16. Collectively the proposed works can improve the runtime of incremental SVM compute-intensive data stream analytics
Interleaved Incremental/Decremental Support Vector Machine for Embedded System
No full textIncremental and Decremental Support Vector Machine (IDSVM) is a widely used incremental learning algorithm that is highly accurate but requires high computational complexity. For IDSVM to be deployed in embedded systems, moving window architecture is needed to limit the number of support vectors in the model. This increases the complexity of the system as data need to be unlearned while learning new data. This work proposes an interleaved IDSVM (IIDSVM) architecture that performs incremental and decremental learning simultaneously. This work targets embedded system platform with limited on-chip memory. The proposed solution is able to get an improvement of 60%-70% in terms of speed while producing similar accuracy with IDSVM
Enabling Data Marketplaces with Multi-Party Computation (MPC): An Exploratory Study investigating the Implication of the Maturation of Multi-Party Computation (MPC) technology to the Architecture and the Threat Landscape of the Data Marketplaces
No full textThe emergence of the Data Marketplaces is the latest iteration in the phenomenon of data-driven transformation of the world. Data marketplaces have emerged as a new form of data-driven business models which enable trading of data between the data owners/providers and data consumers by providing the necessary technological and non-technological infrastructure. These features present an alternative to the cumbersome logistics currently involved in searching, buying and selling data; thus, simplify the data supply chains between the data-driven business entities. However, they suffer to take off into mainstream success because of a myriad of reasons. Of all the reasons, 2 of them are focused in this thesis. Firstly, the difficulty involved in architecturally enabling a data marketplace platform as the prospective enabling technologies are still immature. Secondly, the uncertainty associated with the commodification of data which comprises of the intellectual property enforcement of data (data ownership), privacy and confidentiality breach (threats), regulatory ignorance (implication of GDPR), reluctance of businesses from participating because of the previous reasons et cetera. This reason is collectively referred as due to the uncertainty around the threat landscape of the data marketplaces. Multi-Party Computation (MPC) technology provide a solution to these problems. Through its capabilities to preserve the confidentiality of data architecturally and thereby securing the interests of the data actors with respect to the uncertainty of the threat landscape around data, MPC can enable safe and secure data sharing between data actors. This characteristic of MPC can help data marketplaces to overcome their challenges and foster their realisation. However, since MPC cannot handle the scale of real-life application, it is not mature enough yet to be incorporated into real-life data marketplaces. An EU funded project called SafeDEED: Safe Data-Enabled Economic Development, proposes to overcome the scalability issue and intends to achieve the maturation of MPC for real-life application. Building upon this forecast, a research was conducted to investigate the implication of the maturation of MPC technology towards the 2 problems faced by data marketplaces, architectural and threat landscape; and the same is documented in this thesis.Safe-DEEDManagement of Technology (MoT
Novel Concepts in Cardiac Energy Metabolism: From Biology to Disease
No full textThis eBook is a collection of articles from a Frontiers Research Topic. Frontiers Research Topics are very popular trademarks of the Frontiers Journals Series: they are collections of at least ten articles, all centered on a particular subject. With their unique mix of varied contributions from Original Research to Review Articles, Frontiers Research Topics unify the most influential researchers, the latest key findings and historical advances in a hot research area! Find out more on how to host your own Frontiers Research Topic or contribute to one as an author by contacting the Frontiers Editorial Office: frontiersin.org/about/contac
Adaptive configurable transactional memory for multi-processor FPGA platforms
No full textHardware Transactional memory (HTM) performance is application-specific and is dependent on its version management and conflict management configurations. An adaptive mechanism is needed to adapt its configurations based on multiple application behaviour
A streaming multi-class support vector machine classification architecture for embedded systems
Get PDFPedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated Support Vector Machine (SVM). Computational complexity of SVM classification makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, testing data are mostly stored on external memory. Data are transferred in streams with the maximum bandwidth limited to the bus bandwidth. The hardware implementation for SVM classification needs to be sufficiently fast to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in the streaming architecture. In this work, we propose a streaming-architecture multi-class SVM classification for an embedded system that is fully pipelined and able to process data continuously without any need to throttle data stream input. The proposed design is targeted for embedded platform where testing data is transferred in streams from external memories. The architecture is modeled using Verilog and the evaluation is targeted for Altera Cyclone IV field programmable gate array platform. Performance profiling on the proposed architecture is done with regard to the number of features and support vectors. For validation, the proposed architecture is simulated using ModelSim and the results are compared with LibSVM. Based on the simulation result, the proposed architecture is able to produce a throughput of 1/Nf classification per clock cycle, where Nf is the number of features
Improved Classical Cipher for Healthcare Applications
No full textAbstractE-health is rapidly picking up the gear and providing lots of services. It facilitates novel solutions for the problems suffered by the aged people as well as the people affected with chronic diseases. Apart from the above services, it devotes much interest in personal fitness. The healthcare system makes use of wearable wireless sensors which are implanted in patients, allow the monitoring of the health status at all time. The data collected from the patients transmitted through the network to the clinic or the doctor for a detailed diagnosis. Since healthcare applications are dealing with highly sensitive data, strong cryptographic algorithms should be incorporated for providing confidentiality. However, due to the computational and energy limitations of wireless devices we are forced to implement light weight ciphers which are computationally feasible in achieving confidentiality. This paper proposes a variant of hill cipher having two key matrices to add extra security to health related data
