20,142 research outputs found
Neuro-Inspired Computing with Synaptic and Neuronal Devices
No full textPresented on April 9, 2019 at 12:00 p.m. in the Marcus Nanotechnology Building, Room 1116.Shimeng Yu is an associate professor of electrical and computer engineering at Georgia Tech. Prof. Yu’s research interests are nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications, such as machine/deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security, etc.Runtime: 59:28 minutesNeuro-inspired computing is a new computing paradigm that emulates the neural network for information processing. To enable the large-scale neuromorphic system, it is important to develop compact nanoscale devices to support the synaptic and neuronal functions. In this talk, I will discuss recent progress in this domain that integrates oxide based synaptic and neuronal devices in neuromorphic hardware such as machine/deep learning accelerators. First, I will discuss the desired characteristics of HfO2 based resistive synaptic devices (e.g. analog multilevel states, weight tuning linearity, variation/noises) and NbO2 based oscillation neuron devices, and show the principles of offline training and online training. Next, I will introduce the crossbar array architecture to efficiently implement the weighted sum and weight update operations that are commonly used in the machine/deep learning algorithms, and show array-level experimental demonstrations for these key operations. Lastly, I will show our recent work on doped HfO2 based ferroelectric transistor based synaptic cell design that overcomes the challenges to achieve high training accuracy for online training
Hui tu zhen ben jing shi mu yu jin gang zuan
No full text著作者余好辯, 伍憤時.Cover title.上下卷.On double leaves, East Asian binding.木魚歌文.zhu zuo zhe Yu Haobian, Wu Fenshi.Shang xia juan.Mu yu ge wen
SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations
No full textAlthough several types of architecture combining memory cells and transistors have been used to demonstrate artificial synaptic arrays, they usually present limited scalability and high power consumption. Transistor-free analog switching devices may overcome these limitations, yet the typical switching process they rely on-formation of filaments in an amorphous medium-is not easily controlled and hence hampers the spatial and temporal reproducibility of the performance. Here, we demonstrate analog resistive switching devices that possess desired characteristics for neuromorphic computing networks with minimal performance variations using a single-crystalline SiGe layer epitaxially grown on Si as a switching medium. Such epitaxial random access memories utilize threading dislocations in SiGe to confine metal filaments in a defined, one-dimensional channel. This confinement results in drastically enhanced switching uniformity and long retention/high endurance with a high analog on/off ratio. Simulations using the MNIST handwritten recognition data set prove that epitaxial random access memories can operate with an online learning accuracy of 95.1%.
Yu Takeuchi
No full textYu Takeuchi is serving for JAXA since 2007 and currently working as Associate Senior Administrator at Management and Integration Department of Human Spaceflight Technology Directorate. He is also working as Researcher at the Institute of Space Law of Keio University. He received LL.M. degree from the Institute of Air and Space Law of McGill University in 2015. His main interest is in international space law inter alia the legal aspects of space traffic management and sustainable space development. He is a member of the Air Law Institute of Japan, Japanese Society of International Law, and the International Institute of Space Law (IISL).
Main Works Published in English
- “Toward the International Regime for Space Traffic Management -What to Fix the Current International Regulations-”, (November 5, 2014). Space Traffic Management Conference, Paper 23 (http://commons.erau.edu/stm/2014/wednesday/23).
- “Regulatory Regime for Tomorrow’s Suborbital Space Flights: Point-to-point International Flights”, 56th Colloquium on the Law of Outer Space, 2013.
- “Space Traffic Management as a Guiding Principle of the International Regime of Sustainable Space Activities,” 4 Journal of East Asia and International Law, 2011
- “Japanese Perspective on Legal Issues of Commercial Human Spaceflight” (co-author), 53rd Colloquium on the Law of Outer Space, 2011
- “Legal Points at Issue about NEO Threat Response and International Cooperation” (co-author), 28th International Symposium on Space Technology and Science, 2011
- “From Guideline to International Treaty for Rule of Law concerning Mitigation of Space Debris?” (co-author), 52nd Colloquium on the Law of Outer Space, 2010
Main Works Published in Japanese (title translated into English)
- “What is Space Traffic Management”, Vol. 46, No.9, Journal of the Japanese Institute of International Business Law, 2018.
- Soichiro Kozuka & Masahiko Sato eds., Introduction of Space Law for Entrepreneur (2nd. Ed.), Yuhikaku, 2018. (co-authored)
-“Challenges to International Space Law for Managing Space Traffic”, 55 Kuho (Air Law), 2014.
-“Legal Points as Issues of NEO Threat Response and International Cooperation” (co-author), 3 Spaceguard Research, Japan Spaceguard Association, 2011https://commons.erau.edu/stm-images/1121/thumbnail.jp
Capacitive Synaptor With Overturned Charge Injection for Compute-in-Memory
No full textA capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances (C-on and C-off) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10(7) cycles and retention time of 10(4) sec.
Semiconductor Memory Applications in Radiation Environment, Hardware Security and Machine Learning System
No full textabstract: Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications.
In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level.
Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well.
Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm.
Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Chao cai liao yong yu ya bo chang ju jiao: ge xiang yi xing hao sun cai liao yu ti du guang xue na mi bo dao guan
No full textKwok, Hui Kin = 超材料用於亞波長聚焦 : 各向異性耗損材料與梯度光學納米波導管 / 郭栩健.Thesis M.Phil. Chinese University of Hong Kong 2015.Includes bibliographical references (leaves 67-69).Abstracts also in Chinese.Title from PDF title page (viewed on 26, September, 2016).Kwok, Hui Kin = Chao cai liao yong yu ya bo chang ju jiao : ge xiang yi xing hao sun cai liao yu ti du guang xue na mi bo dao guan / Guo Xujian
Yi ge zai Jianada wei qi si xing qi de Ying yu ke cheng de yu wen ji wen hua xue xi
No full textChan, Sin Yu.Thesis M.Phil. Chinese University of Hong Kong 2015.Includes bibliographical references (leaves 260-268).Abstracts also in Chinese; some appendixes in Chinese.Title from PDF title page (viewed on 11, November, 2016).Chan, Sin Yu
Scalable in-memory clustered annealer with temporal noise of FinFET for the travelling salesman problem
No full textIntractability of Optimal Multi-Robot Path Planning on Planar Graphs
No full textWe study the computational complexity of optimally solving multi-robot path planning problems on planar graphs. For four common time- and distance-based objectives, we show that the associated path optimization problems for multiple robots are all NP-complete, even when the underlying graph is planar. Establishing the computational intractability of optimal multi-robot path planning problems on planar graphs has important practical implications. In particular, our result suggests the preferred approach toward solving such problems, when the number of robots is large, is to augment the planar environment to reduce the sharing of paths among robots traveling in opposite directions on those paths. Indeed, such efficiency boosting structures, such as highways and elevated intersections, are ubiquitous in robotics and transportation applications.Peer reviewe
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