557 research outputs found
sj-pdf-1-ajs-10.1177_03635465231180323 – Supplemental material for Efficacy and Safety of Stempeucel in Osteoarthritis of the Knee
No full textSupplemental material, sj-pdf-1-ajs-10.1177_03635465231180323 for Efficacy and Safety of Stempeucel in Osteoarthritis of the Knee by Pawan Kumar Gupta, Sunil Maheshwari, Joe Joseph Cherian, Vijay Goni, Arun Kumar Sharma, Sujith Kumar Tripathy, Keerthi Talari, Vivek Pandey, Parag Kantilal Sancheti, Saurabh Singh, Syamasis Bandyopadhyay, Naresh Shetty, Surendra Umesh Kamath, Purohit Sharad Prahaldbhai, Jijy Abraham, Suresh Kannan, Samatha Bhat, Shivashankar Parshuram, Vinayaka Shahavi, Akhilesh Sharma, Nikhil N. Verma and Uday Kumar in The American Journal of Sports Medicine</p
Clock multiplication techniques for high-speed I/Os
No full textGeneration of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored.
First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.
Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB.
Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01The student, Romesh Kumar Nandwana, accepted the attached license on 2017-04-17 at 15:09.The student, Romesh Kumar Nandwana, submitted this Dissertation for approval on 2017-04-17 at 15:42.This Dissertation was approved for publication on 2017-04-19 at 08:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #10816 on 2017-08-10 at 15:05:48Made available in DSpace on 2017-08-10T20:32:59Z (GMT). No. of bitstreams: 3
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Previous issue date: 2017-04-19Embargo set by: Colleen Fallaw for item 102771
Lift date: 2019-08-10T21:27:21Z
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Energy-efficient wireline transceivers
No full textPower-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50.The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42.This Dissertation was approved for publication on 2016-09-30 at 13:20.DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3
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Previous issue date: 2016-09-30Embargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:02:22Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:03:32Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:05:02Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:06:55Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 98665 on 2019-03-02T10:15:18Z
Women’s Entrepreneurship in Patriarchal Societies: The Case of Women’s Cooperatives in Turkey
No full textThis chapter explores the limits of and prospects for women’s entrepreneurship in patriarchal communities. The chapter investigates the patriarchal institutions and societal norms which work against women’s entrepreneurial activities and women’s presence in socioeconomic life in general. It also delves into women’s strategies to bargain, deal, and cope with patriarchal norms and institutions. The research is based on an extensive fieldwork on the case of Turkey, a country replete with patriarchal norms and institutions. The author conducts in-depth semi-structured interviews with members of women’s cooperatives throughout Turkey to better understand and explain the obstacles against women’s entrepreneurship in patriarchal societies and how women deal with these obstacles in their daily, entrepreneurial practices. In light of the fieldwork findings, the chapter concludes with policy implications and recommendations for more egalitarian and prosperous societies
Criptografia de curvas elípticas sobre extensões de corpos finitos
No full textUm sistema de criptografia de curvas elípticas se baseia no uso do algoritmo de criptografia de chave pública de ElGamal sobre o grupo de pontos de uma curva elíptica definida sobre um corpo finito. Em geral, os protocolos de segurança para computadores utilizam apenas curvas elípticas definidas sobre corpos de cardinalidade prima p ou 2k. Neste trabalho é proposto o uso do grupo de pontos em extensões finitas do corpo de definição de uma curva elíptica; para isso é desenvolvido um algoritmo de adição de pontos utilizando o endomorfismo de Frobenius que, em certa classe de curvas, é mais eficiente que o algoritmo tradicional. Também é descrito um método eficiente para obter a ordem do grupo de pontos destas curvas. Finalmente é apresentado uma generalização do algoritmo de primalidade de Miller para a obtenção de polinômios irredutível sobre corpos finitos, essenciais para o trabalho com extensões destes corpos, e os resultados obtidos a partir da implementação destes algoritmos.An elliptic curve cryptosystem is based on the use of the encryption algorithm of public key of ElGamal on the group of points of the elliptic curve over a finite field. In general, the security protocols for computers use only elliptic curves defined over fields of cardinality prime p or 2k. In this work, is proposed the use of the group of points in finite extensions of the field of definition of the elliptic curve; for this an algorithm of addition of points using the endomorphism of Frobenius, which is more efficient than the traditional algorithm to a certain family of curves, is developed. An eficient method to obtain the order of the group of points of these curves is also described. Finally, a generalization of the Millers algorithm of primality is given to obtain irreducible polynomals over finite fields, necessary to work with extensions of these fields, and the results obtaind based on implementation of these algorithms
Measuring core inflation in India: An asymmetric trimmed mean approach
No full textThe paper seeks to obtain an optimal asymmetric trimmed mean-based core inflation measure in the class of trimmed mean measures when the distribution of price changes is leptokurtic and skewed to the right for any given period. Several estimators based on asymmetric trimmed mean approach are constructed and estimates generated by use of these estimators are evaluated on the basis of certain established empirical criteria. The paper also provides the method of trimmed mean expression "in terms of percentile score." This study uses 69 monthly price indices which are constituent components of Wholesale Price Index for the period, April 1994 to April 2009, with 1993 - 1994 as the base year. Results of the study indicate that an optimally trimmed estimator is found when we trim 29.5% from the left-hand tail and 20.5% from the right-hand tail of the distribution of price changes
The properties of inflation expectations: Evidence for India
No full textEmpirical inferences about particular forms of agents’ inflation expectations are crucial for the conduct of monetary policy. This paper is an attempt to explore the properties of the Reserve Bank of India’s survey data of households’ inflation expectations. The paper shows that survey respondents do not form expectations rationally, regardless of the reference measures of inflation used. Further, results indicate that inflation expectations are formed purely in backward-looking manner, suggesting that the Reserve Bank of India (RBI) has a low degree of credibility within the survey respondents. The study then formulates a model to identify individual elements of the backward-looking expectations in the data. The results suggest that the respondents’ short term expectations for WPI inflation are purely naïve type of expectations, only influenced by respondents earlier period expectations. In the case of CPIIW inflation, the results however suggest that the short-term expectations are not purely naïve type, but also contain adaptive as well as a static forms of expectations. This means that respondents consider their previous forecast errors about CPIIW inflation and draw recent price developments in the CPIIW while forming their overall short-term inflation expectations. This finding provides some formal evidence that the CPI based inflation measure is better suited, than WPI inflation, as a nominal anchor in the RBI’s recent transition to inflation targeting regime. JEL classification: D84, E31, E52, E37, Keywords: Inflation, Inflation expectations, Survey data, Price index, Monetary policy, Forecastin
Design of energy efficient high speed I/O interfaces
No full textThe student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs.
A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.
Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers.
We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01The student, Mrunmay Vyankatesh Talegaonkar, submitted this Dissertation for approval on 2016-03-11 at 14:46.This Dissertation was approved for publication on 2016-03-15 at 08:51.DSpace SAF Submission Ingestion Package generated from Vireo submission #9102 on 2016-07-07 at 14:16:14Made available in DSpace on 2016-07-07T21:14:23Z (GMT). No. of bitstreams: 3
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Previous issue date: 2016-03-15Embargo set by: Seth Robbins for item 93225
Lift date: 2018-07-07T21:14:52Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 93225
Lift date: 2018-07-07T21:18:16Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 93225 on 2018-07-08T09:15:16Z
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