38 research outputs found
Novel multi-electrode probe with three dimensional spatial resolution for simultaneous recording/stimulation in long-term adaptive deep brain stimulaton
No full textWhen treating neurological disorders such as Parkinson’s Disease (PD) modern technologies experience many deficiencies and/or limitations that researchers have been working towards improving. The problems that occur with modern devices are inadequate mechanical robustness, glial scarring due to tissue damage, reduced target area localization, and inability to simultaneously record/stimulate in vivo post implantation. The research presented here resolves the issues stated above, delivering the design of a novel Multi-Electrode Probe with 3-D spatial resolution and an on-board preamplification/filtering chip capable of simultaneous recording/stimulation. The probe has been modeled in Wildfire Pro/Engineer 4.0 and Finite Element Analysis (FEA) was performed in COMSOL Multiphysics 3.4. The neural chip which consists of both analog and digital circuitry was designed with Taiwan Semiconductor’s (TSMC) 0.18µm CMOS technology. The very large scale integration (VLSI) design and simulation was performed in Cadence Schematic and Spectre, respectively. The aforementioned work was done in hopes of delivering a neural probe that can eventually be used in a closed loop system for Adaptive Deep Brain Stimulation treatment.Ph.D.Includes bibliographical referencesIncludes vitaby Ryan M. Elkhol
NOVEL NEUROCHIP DESIGN IMPLEMENTING ALOPEX FOR USE IN AN AUTOMATED DEEP BRAIN STIMULATION SYSTEM FOR PARKINSON’S PATIENTS
No full textAnd approved b
Endoscopic Resection of Submucosal Lesions of the Upper GI Tract: Full-Thickness Resection (EFTR) and Submucosal Tunneling Resection (STER)
No full textDigital enhancement techniques for fractional-N frequency synthesizers
No full textMeeting the demand for unprecedented connectivity in the era of internet-of-things (IoT) requires extremely energy efficient operation of IoT nodes to extend battery life. Managing the data traffic generated by trillions of such nodes also puts severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and clocking modules by exploring design techniques at both the architectural and circuit levels.
In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1ps resolution. Fabricated in 65nm CMOS process, the prototype PLL achieves better than -106dBc/Hz in-band noise and 3MHz PLL bandwidth at 4.5GHz output frequency using 50MHz reference. The PLL achieves excellent jitter performance of 490fsrms, while consumes only 3.7mW. This translates to the best reported jitter-power figure-of-merit (FoM) of -240.5dB among previously reported FNPLLs.
Phase noise performance of ring oscillator based digital FNPLLs is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the TDC, ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their FoM that quantifies the power-jitter tradeoff is at least 25dB worse than their LC-oscillator based FNPLL counterparts. In the second part of this thesis, we seek to close this performance gap by extending PLL bandwidth using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. A prototype was implemented in a 65nm CMOS process operating over a wide frequency range of 2.0GHz-5.5GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9psrms integrated jitter while consuming only 4mW at 5GHz output. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference and its FoM is -228.5dB, which is at about 20dB better than previously reported ring-based digital FNPLLs.
In the third part, we propose a new multi-output clock generator architecture using open loop fractional dividers for system-on-chip (SoC) platforms. Modern multi-core processors use per core clocking, where each core runs at its own speed. The core frequency can be changed dynamically to optimize for performance or power dissipation using a dynamic frequency scaling (DFS) technique. Fast frequency switching is highly desirable as long as it does not interrupt code execution; therefore it requires smooth frequency transitions with no undershoots. The second main requirement in processor clocking is the capability of spread spectrum frequency modulation. By spreading the clock energy across a wide bandwidth, the electromagnetic interference (EMI) is dramatically reduced. A conventional PLL clock generation approach suffers from a slow frequency settling and limited spread spectrum modulation capabilities. The proposed open loop fractional divider architecture overcomes the bandwidth limitation in fractional-N PLLs. The fractional divider switches the output frequency instantaneously and provides an excellent spread spectrum performance, where precise and programmable modulation depth and frequency can be applied to satisfy different EMI requirements. The fractional divider has unlimited modulation bandwidth resulting in spread spectrum modulation with no filtering, unlike fractional-N PLL; consequently it achieves higher EMI reduction. A prototype fractional divider was implemented in a 65nm CMOS process, where the measured peak-to-peak jitter is less than 27ps over a wide frequency range from 20MHz to 1GHz. The total power consumption is about 3.2mW for 1GHz output frequency. The all-digital implementation of the divider occupies the smallest area of 0.017mm2 compared to state-of-the-art designs.
As the data rate of serial links goes higher, the jitter requirements of the clock generator become more stringent. Improving the jitter performance of conventional PLLs to less than (200fsrms) always comes with a large power penalty (tens of mWs). This is due to the PLL coupled noise bandwidth trade-off, which imposes stringent noise requirements on the oscillator and/or loop components. Alternatively, an injection-locked clock multiplier (ILCM) provides many advantages in terms of phase noise, power, and area compared to classical PLLs, but they suffer from a narrow lock-in range and a high sensitivity to PVT variations especially at a large multiplication factor (N). In the fourth part of this thesis, a low-jitter, low-power LC-based ILCM with a digital frequency-tracking loop (FTL) is presented. The proposed FTL relies on a new pulse gating technique to continuously tune the oscillator's free-running frequency. The FTL ensures robust operation across PVT variations and resolves the race condition existing in injection locked PLLs by decoupling frequency tuning from the injection path. As a result, the phase locking condition is only determined by the injection path. This work also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25mm2. The prototype ILCM multiplies the reference frequency by 64 to generate an output clock in the range of 6.75GHz-8.25GHz. A superior jitter performance of 190fsrms is achieved, while consuming only 2.25mW power. This translates to a best FoM of -251dB.
Unlike conventional PLLs, ILCMs have been fundamentally limited to only integer-N operation and cannot synthesize fractional-N frequencies. In the last part of this thesis, we extend the merits of ILCMs to fractional-N and overcome this fundamental limitation. We employ DTC-based QNC techniques in order to align injected pulses to the oscillator's zero crossings, which enables it to pull the oscillator toward phase lock, thus realizing a fractional-N ILCM. Fabricated in 65nm CMOS process, a prototype 20-bit fractional-N ILCM with an output range of 6.75GHz-8.25GHz consumes only 3.25mW. It achieves excellent jitter performance of 110fsrms and 175fsrms in integer- and fractional-N modes respectively, which translates to the best-reported FoM in both integer- (-255dB) and fractional-N (-252dB) modes. The proposed fractional-N ILCM also features the first-reported rapid on/off capability, where the transient absolute jitter performance at wake-up is bounded below 4ps after less than 4ns. This demonstrates almost instantaneous phase settling. This unique capability enables tremendous energy saving by turning on the clock multiplier only when needed. This energy proportional operation leverages idle times to save power at the system-level of wireline and wireless transceivers.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Ahmed Elkholy, accepted the attached license on 2016-11-16 at 16:12.The student, Ahmed Elkholy, submitted this Dissertation for approval on 2016-11-16 at 16:30.This Dissertation was approved for publication on 2016-11-17 at 08:48.DSpace SAF Submission Ingestion Package generated from Vireo submission #10258 on 2017-02-28 at 14:41:35Made available in DSpace on 2017-03-01T17:01:19Z (GMT). No. of bitstreams: 6
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Previous issue date: 2016-11-17Embargo set by: Seth Robbins for item 98689
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Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 98689 on 2019-03-02T10:15:27Z
Double-balloon enteroscopy (DBE) in patients presenting with obscure gastrointestinal bleeding (OGIB)
No full textImpact of enhanced depression screening in primary care: evaluation of a quality improvement project
No full textPurpose of Project: The aim of this quality improvement project was to evaluate the impact of the Patient Health Questionnaire-9 (PHQ-9) in identifying persons with depression and to develop recommendations on improving the process of screening and managing depression in a primary care practice. A primary care practice in suburban New Jersey wanted to enhance its diagnosis and identification of depression among its clinic population. The practice site switched their previous standard of using a PHQ-2 to a PHQ-9 in March 2022. This project aimed to assess the difference in the number of patients identified with depression using the more elaborate PHQ-9 and to make recommendations to enhance their mental health screening protocol.
Methodology: Retrospective chart review was used to assess the differences in the rates of depression identified using the PHQ-9. Charts were reviewed for 3 months prior to implementation of the PHQ-9 and for 3 months after implementation of the screening tool.
Results: A total of 394 charts were reviewed for the entire project. In the pre-intervention phase, 5 individuals out of 158 persons screened, had a positive screen for depression. In the post-intervention phase 40 out of 191 screened positive for depression.
Implications for Practice: Use of a more elaborate screening tool, may enhance detection in this primary care practice. Clinicians should consider using the PHQ-9 if time and capacity allow for a more in-depth screening.
Keywords: depression screening, PHQ-2, PHQ-9, primary care.D.N.P.Includes bibliographical reference
Merging Prospect Theory with the Analytic Hierarchy Process: Applications to Technology Markets
No full textabstract: This thesis presents a model for the buying behavior of consumers in a technology market. In this model, a potential consumer is not perfectly rational, but exhibits bounded rationality following the axioms of prospect theory: reference dependence, diminishing returns and loss sensitivity. To evaluate the products on different criteria, the analytic hierarchy process is used, which allows for relative comparisons. The analytic hierarchy process proposes that when making a choice between several alternatives, one should measure the products by comparing them relative to each other. This allows the user to put numbers to subjective criteria. Additionally, evidence suggests that a consumer will often consider not only their own evaluation of a product, but also the choices of other consumers. Thus, the model in this paper applies prospect theory to products with multiple attributes using word of mouth as a criteria in the evaluation.Dissertation/ThesisMasters Thesis Applied Mathematics 201
Probing the history of galaxy clusters with metallicity and entropy measurements
No full textThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Physics, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 217-220).Galaxy clusters are the largest gravitationally bound objects found today in our Universe. The gas they contain, the intra-cluster medium (ICM), is heated to temperatures in the approximate range of 1 to 10 keV, and thus emits X-ray radiation. Studying the ICM through the spatial and spectral analysis of its emission returns the richest information about both the overall cosmological context which governs the formation of clusters, as well as the physical processes occurring within. The aim of this thesis is to learn about the history of the physical processes that drive the evolution of galaxy clusters, through careful, spatially resolved measurements of their metallicity and entropy content. A sample of 45 nearby clusters observed with Chandra is analyzed to produce radial density, temperature, entropy and metallicity profiles. The entropy profiles are computed to larger radial extents than in previous Chandra analyses. The results of this analysis are made available to the scientific community in an electronic database. Comparing metallicity and entropy in the outskirts of clusters, we find no signature on the entropy profiles of the ensemble of supernovae that produced the observed metals. In the centers of clusters, we find that the metallicities of high-mass clusters are much less dispersed than those of low-mass clusters. A comparison of metallicity with the regularity of the X-ray emission morphology suggests that metallicities in low-mass clusters are more susceptible to increase from violent events such as mergers. We also find that the variation in the stellar-to-gas mass ratio as a function of cluster mass can explain the variation of central metallicity with cluster mass, only if we assume that there is a constant level of metallicity for clusters of all masses, above which the observed galaxies add more metals in proportion to their mass.by Tamer Yohanna Elkholy.Ph.D
