1,720,989 research outputs found
June 1995 CSTR-95-010
No full textNeil Davies University of Bristol Andrew Jones SGS-Thomson Microelectronics In effectively applying any novel technology, the C104 switch being such an example, there is a need to quickly build a corpus of knowledge as to the best ways of using that technology and what can be reasonably expected of it. The general aim of the Macrame project is to perform this characterisation for the C104. This extended abstract describes ongoing work to building GSPN models of the C104 switching behaviour for ATM-like networks. The aim is to create computationally less expensive ways of modelling configurations of this switch without resorting to complete, behavioural models of the switching fabric
Industrial experience using rule-driven retargetable code generation for multimedia applications
No full textInternational audienceThe increasing usage of application-specific instruction set processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicated compilers. A rule-driven approach to code generation may have benefits over model-based approaches as the user is not confined to the capabilities supported by the model. However, the sole use of transformation rules may or may not be sufficient in optimization abilities depending on the target architecture. This paper outlines experiences with a rule-driven code generation approach for two applications in audio and video processing. The first is a controller for the VideoPhone codec at SGS-Thomson Microelectronics. The second is a VLIW (very large instruction word) processor for high-fidelity and MPEG audio at Thomson Consumer Electronic Components. The experience has shown that a rule-driven approach to compilation is applicable to both the controller and VLIW architectures; however, is limited in optimization abilities for the latter
An embedded system case study: the firmware development environment for a multimedia audio processor
No full textThis paper outlines a case study at SGS-Thomson Microelectronics on the development of a firmware development environment in cooperation with Thomson Consumer Electronics Components. The environment is for an embedded processor used for audio decompression algorithms including: MPEG2 Dolby AC-3 Surround, and Dolby Pro-logic. The enabling component of the firmware environment is a retargetable compiler which maps high-level algorithms onto the embedded processor. Although compilation is the critical technology this experience has shown that it is insufficient and that other supporting design tools are also important. For this project, that environment includes an instruction-set simulator, a source-level debugger, a custom linker and a compiler validation strategy. The methodologies are outlined in this paper with an emphasis on the lessons learned in this hardware-software team developmen
Régulation d amplificateurs de puissance sous condition d ondes stationnaires en CMOS 65nm pour des applications WLAN à 60GHz
No full textAvec l apparition d applications grand-public, comme le Wireless-HD, les fréquences millimétriques nécessitent l utilisation de technologies CMOS faible coût. Cependant, avant d être commercialisés, les transmetteurs mmW doivent être suffisamment résistants notamment à la désadaptation d impédance entre l amplificateur de puissance (AP) et l antenne qui peut résulter d un obstacle dans le champ proche de l antenne. Une telle désadaptation d impédance se traduit par l apparition d ondes stationnaires qui peuvent engendrer des dommages irrémédiables sur l AP. Cette thèse propose une architecture innovante de régulation qui vise à protéger l AP de telles dégradations tout en optimisant ses performances. La désadaptation d impédance peut être évaluée en intégrant plusieurs détecteurs de puissance entre l AP et l antenne. Une boucle de régulation numérique peut ensuite établir une stratégie d optimisation des performances de l AP. Cette thèse s intéresse particulièrement aux circuits de détection de puissance qui captent la désadaptation d impédance de l antenne. Réalisé en technologie CMOS 65nm de STMicroelectronics, le détecteur de puissance présente 25dB de dynamique à 60GHz et est capable de détecter jusqu à 3 :1 de TOS. Ces détecteurs de puissance ont ensuite été intégrés dans un second circuit avec un AP et des convertisseurs (CAN & CNA). Une boucle de régulation agissant sur le gain de l AP permet ainsi de garder une puissance de sortie constante quelle que soit l impédance d antenne tandis qu une seconde boucle protège l AP de la destruction. Cette thèse couvre également deux projets développés en parallèle de l architecture de régulation de TOS. D abord est proposée une nouvelle architecture de convertisseur analogique numérique logarithmique, basée sur l architecture d amplificateur logarithmique à compression progressive. Ensuite, une co-simulation sous ADS d un AP RF/mmW avec sa boucle de régulation numérique permet de simuler l AP à TOS régulé.With the emergence of mass-market applications, such as Wireless-HD, low-cost CMOS technologies are requested to democratize the use of mmW frequencies. However, before being commercialized, mmW transmitters have to ensure sufficient reliability. One major reliability issue lies in the impedance mismatch between the power amplifier (PA) and the antenna, which can result from wave propagation obstacles in the close vicinity of the antenna. Such impedance mismatch generates standing waves, which can cause irreversible damage on the power amplifier. This thesis aims to propose an innovating regulation architecture that could protect the power amplifier from such deterioration and optimize its performance. By integrating several power detectors between the PA and the antenna, the impedance mismatch can be evaluated. Using this information, a digital regulation loop could then elaborate a complete strategy in order to optimize the PA performance. This thesis notably investigates the power detection circuits, which should sense the antenna impedance mismatch. A circuit realization in 65nm CMOS process from STMicroelectronics shows that the power detector provides 25dB dynamic range at 60GHz and is able to detect up to 3:1 VSWR. A second circuit realization integrates a power amplifier, the power detection circuits and data converters (ADC & DAC). The regulation loop acts on the power amplifier gain to keep a constant PA output power whatever the antenna impedance is. A second loop is also integrated, which protects the PA from destruction. This thesis also covers two alternative projects developed simultaneously to the VSWR-regulated PA architecture. First, a novel architecture of Logarithmic-Analog-to-Digital-Converter is proposed, which is based on the progressive compression architecture of logarithmic amplifier. Then the simulation aspect of the VSWR-regulated PA is investigated through an ADS co-simulation of an RF/mmW PA with its mixed-signal regulation loop.LILLE1-Bib. Electronique (590099901) / SudocSudocFranceF
Synthèse et caractérisation de silicium cristallin par croissance VLS pour l'intégration 3D séquentielle de transistors MOS
No full textL intégration en trois dimensions se présente comme une alternative à la réduction des dimensions pour poursuivre l augmentation continuelle de la densité des composants. Elle permet également de réduire le délai dans les interconnexions. Un autre avantage, non négligeable, est la possibilité d ajouter de nouvelles fonctionnalités sur les niveaux supérieurs. Cependant, l empilement de composants et leur interconnexion verticale doivent faire face à deux difficultés majeures. Tout d abord, l obtention d un substrat semi-conducteur monocristallin de haute qualité sur une couche diélectrique doit s effectuer sans détériorer les composants réalisés précédemment, en respectant une température limite. Ensuite, les composants supérieurs doivent être alignés avec précision par rapport au niveau inférieur, et doivent être intégrés tout en respectant le budget thermique imposé par les transistors déjà existants.Dans ce contexte, cette thèse s attache à démontrer une approche innovante pour la synthèse de la couche active supérieure, en utilisant la croissance par CVD catalytique (VLS) confinée et guidée à l intérieur d une cavité. Ce manuscrit est composé de 4 chapitres : Le premier chapitre rappelle les notions de base des dispositifs et technologies MOS et fournit une analyse des différentes sources de dégradation liées à la miniaturisation. L intégration en trois dimensions est ensuite introduite, accompagnée des différents procédés de fabrication. Une autre méthode de synthèse de silicium monocristallin plus originale est proposée : la croissance VLS. Le deuxième chapitre est consacré à la croissance VLS de nanofils de silicium sur substrat amorphe. L aspect théorique et l optimisation de la recette de croissance sont détaillés. Ainsi, des nanofils de silicium rectilignes avec des diamètres et des positions parfaitement contrôlés sont obtenus grâce à des motifs catalytiques définis par lift-off. Dans le troisième chapitre, une méthode de fabrication de cavité compatible avec l approche 3D est proposée afin de contrôler avec précision les dimensions et la position du silicium formée par VLS. Une étude de la croissance de nanolames par VLS confinée dans ces cavités est proposée. Deux techniques de caractérisation structurale complémentaires (EBSD, STEM) sont utilisées afin d analyser en détail la structure du silicium. Le dernier chapitre présente la fabrication de transistors MOS en utilisant les lames de silicium produites par VLS comme canal de conduction. L intégration de transistors à grille arrière nous a permis de déterminer les paramètres élémentaires du transport et de les comparer à ceux des substrats SOI commerciaux.Three-dimensional integration of semiconductor devices is perceived as an alternative to device scaling in order to continue the increasing of the devices density. Moreover, it can reduce interconnect delay. Finally it allows the addition of different technologies in the back-end of the line, therefore enabling more applications. 3D integration requires the stacking of active layers alternated with interlayer dielectrics (ILD). The first challenge consists in growing crystal quality semiconductor starting on an amorphous substrate. The second difficulty concerns the device integration: the alignment registration between several active layers must be accurate and the temperature of fabrication is limited by the silicidation thermal budget of transistors integrated in inferior layers. In this context, this thesis demonstrates the synthesis of the crystalline silicon active layers using a new method, namely, the catalytic confined and guided Vapor-Liquid-Solid (VLS) growth.This manuscript is organized into four chapters: The first chapter develops fundamental notions associated to MOS devices and technologies, and provides an analysis of parasitic effects due to miniaturization. Three-dimensional integration is subsequently introduced with a detailed discussion on fabrication process. A new method is proposed to grow crystal semiconductor on an amorphous layer: the VLS growth. The second chapter is devoted to the VLS growth of silicon nanowires on an amorphous substrate. The theoretical aspect and the recipe optimization are developed. The localization of nanowires is controlled by catalyst patterns made by lift-off. In the third chapter, one method of cavity fabrication is proposed in order to control with accuracy dimensions and position of silicon blade synthetized by VLS. The single crystalline nature of silicon has been checked based on complementary techniques: Electron Back-Scattered Diffraction (EBSD) and Scanning Transmission Electron Microscopy (STEM). The last chapter presents the electrical characterization of VLS grown silicon nanoribbons. For that sake, pseudo-MOS transistors have been fabricated using VLS grown silicon blade as conduction channel and back-gate control. The characteristics of these transistors were extracted and compared to that of commercial SOI thin films.LILLE1-Bib. Electronique (590099901) / SudocSudocFranceF
A dedicated circuit for real time motion estimation
No full textInternational audienceThis paper presents a circuit dedicated to real-time motion estimation in video compression systems. It computes motion vectors in the range -8/+7 for 8x4n and 16x4n sized blocks at pixel rates up to 18 MHz. The architecture is based on a 128 processor systolic array. This 270000 transistor IC uses a 2 metal layer 1.2um CMOS process
Implementing new dispatching rules at SGS Thomson Microelectronics
No full textThis paper reports a real-life manufacturing case study in the short term production planning and control for a very large scale integrated (VLSI) circuit manufacturing production unit Dispatching in VLSI manufacturing is a crucial issue, since often binding constraints are set on the delivery dates by the customers downstream in the supply chain, while manufacturers , due to the huge fixed cost of capital goods, must ensure the full utilization of their shop floors. The complexity of the manufacturing technology and the re-entrant nature of the resulting production flows further add difficulties to the problem. Starting from a shop floor scheduling based on simple dispatching rules, e.g. FIFO rule, or the well-known 'minimum set-up' criterion, workcentres have been firstly grouped according to their nature, then they have been classified according to their criticality in terms of production capacity and flexibility. Finally, for each class, a customized, yet suitable to be implemented, dispatching rule is proposed and tested through a wide simulation campaign. Experimental results show that the proposed dispatching approach leads to a superior overall output and, at the same time, to an increased delivery timeliness
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