1,720,960 research outputs found
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
No full textIn many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in allowing the shutdown of the islands. In this paper, we present a synthesis approach to obtain customized application-specific Networks on Chips (NoCs) that can support the shutdown of voltage islands. Our results on realistic SoC benchmarks show that the resulting NoC designs only have a negligible overhead in SoC active power consumption (average of 3%) and area (average of 0.5%) to support the shutdown of islands. The shutdown support provided can lead to a significant leakage and hence total power savings
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
No full textThree-dimensional integrated circuits (3D-ICs) are
a promising approach to address the integration challenges
faced by current systems on chips (SoCs). Designing an efficient
network on chip (NoC) interconnect for a 3-D SoC that meets
not only the application performance constraints but also the
constraints imposed by the 3-D technology is a significant
challenge. In this paper, we present a design tool, SunFloor
3D, to synthesize application-specific 3-D NoCs. The proposed
tool determines the best NoC topology for the application,
finds paths for the communication flows, assigns the network
components to the 3-D layers, and places them in each layer. We
perform experiments on several SoC benchmarks and present a
comparative study between 3-D and 2-D NoC designs. Our studies
show large improvements in interconnect power consumption
(average of 38%) and delay (average of 13%) for the 3-D NoC
when compared to the corresponding 2-D implementation. Our
studies also show that the synthesized topologies result in large
power (average of 54%) and delay savings (average of 21%) when
compared to standard topologies
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands
No full textIn many of today’s system-on-chip (SoC) designs, the
cores are partitioned into multiple voltage and frequency islands
(VFIs), and the global interconnect is implemented using a packetswitched
network on chip (NoC). In such VFI-based designs,
the benefits of 3-D integration in reducing the NoC power or
delay are unclear, as a significant fraction of power is spent in
link-level synchronization, and stacked designs may impose many
synchronization boundaries. In this brief, we show the quantitative
benefits of the 3-D technology on NoC power and delay values
for such application-specific designs. We show a design flow for
building application-specific NoCs for both 2-D and 3-D SoCs with
multiple VFIs. We present a detailed case study of NoCs designed
using the flow for a mobile platform. Our results show that power
savings strongly depend on the number of VFIs used (up to 32%
reduction). This motivates the need for an early architectural
space exploration, as allowed by our flow. Our experiments also
show that the reduction in delay is only marginal when moving
from 2-D to 3-D systems (up to 11%), if both are designed
efficiently
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control
No full textNetworks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To match the application characteristics, customized irregular topologies and routing functions are used. With wormhole flow control and custom irregular NoC topologies, deadlocks can occur during system operation. Ensuring a deadlock free operation of custom NoCs is a major challenge. In this paper, we address this important issue and present a method to remove deadlocks in application-specific NoCs. Our method can be applied to any NoC topology and routing function, and the potential deadlocks are removed by adding minimal number of virtual or physical channels. Experiments on a variety of realistic benchmarks show that our method results in a large reduction in the number of resources needed (88% on average) and NoC power consumption, area reduction (66% area savings on average) when compared to the state-of-the-art deadlock removal methods
A Floorplan-aware Interactive Tool Flow for NoC Design and Synthesis
No full textIn this paper we present a floorplan-aware toolchain for NoC
design and synthesis integrated with a graphical front-end. The
resulting design methodology is highly automated yet entails rich
interaction with the user, spanning across traffic flow specification,
topology synthesis and physical floorplanning, with back-annotation
capabilities and opportunities for incremental design. We exploit the
proposed tool to implement some NoC-based case studies. We show
that not only a great amount of time and effort can be saved thanks
to the easy-to-use proposed environment, but also that the quality of
the final netlist improves due to the optimizations unlocked by the
early-stage interaction among the designer and the proposed
toolchain
Networks on Chips: From research to products
No full textResearch on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
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