1,720,972 research outputs found
Transistor-Level Programmable Fabric
No full textWe introduce a CMOS computational fabric consisting of carefully arranged regular rows and
columns of transistors which can be individually configured and appropriately interconnected in
order to implement a target digital circuit. This TRAnsistor-level Programmable (TRAP) fabric
allows simultaneous storage of four independent configurations, along with the ability to
dynamically switch between them in a small fraction of a clock cycle. We term this board-level
virtualization in that each configuration, in effect, implements an independent chip. TRAP also
supports chip-level virtualization in which a single IC design is partitioned over a set of
configurations and the computation cycles from one configuration to the next in the set. This allows
a design that requires more computational logic than physically available on the TRAP chip to be
nonetheless executable. TRAP also features rapid partial or full modification of any one of the
stored configurations in a time proportional to the number of modified configuration bits through
the use of hierarchically arranged, high throughput, pipelined memory buffers. TRAP supports
libraries of cells of the same height and variable width, just as in a typical standard cell circuit. We
developed a complete Computer-aided Design (CAD) tool flow for programming TRAP chips. A
prototype 3mm X 3mm TRAP chip was fabricated using the Global Foundries 55nm process. We
show that TRAP has substantially better area efficiency compared to a leading industrial FPGA
and would, therefore, be ideal for embedded FPGA (eFPGA) applications
Standard Cell Library Design with Transistor Folding Using 65nm Technology by Global Foundries
No full textWe use the concept of transistor folding to design some of the cells in the cell library. Transistor folding, also known as fingering of MOSFETs, is used when we require cells with larger drive strengths. By keeping the beta ratio (Wp / Wn) fixed, a greater number of transistors are arranged in parallel. Whenever there is a requirement of large current to the load, this technique of transistor folding is employed. The major advantage of using this technique is that it drastically reduces the resistances. To be more precise, if there are N transistors in parallel then the overall resistance reduces by a factor of N. Folding is used to optimize the resistance of the gate poly along the width of the transistor. Gate poly is driven from one end; hence, there is a reason to have a guideline that states maximum width of single finger. Folding is the only way to meet this guideline for large transistors. Our physical library has 16 functions, each with several drive sizes, giving a total of 83 cells. These 16 functions are comprised of simple functions as well as some complex functions. The complex functions were included in the library design because adding these complex functions improves the synthesis performance. Various parameters such as layout area, fall-time, rise-time, fall-transition time, and rise transition time are obtained during library characterization. The designed cells were characterized using Synopsys Siliconsmart ACE and we were able to automatically place and route various designs using Cadence Encounter. The static timing analysis was performed using Synopsys PrimeTime
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Thermal-aware Placement and High Level Synthesis for Hardware Security
No full textShrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field
Programmable Gate Arrays (FPGAs),coarse-grained runtime reconfigurable architectures
(CGRRAs) and application-specific integrated circuits (ASICs), making them increasingly
sensitive to aging effects such as Negative Bias Temperature Instability (NBTI).
This dissertation deals with this problem and provide a reliability-aware floorplanner which
is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs)
and seeks to extend their mean time to failure (MTTF) by balancing the usage of processing
elements (PEs). The proposed method is based on a Mixed Integer Linear Programming
(MILP) formulation, the solution to which produces appropriately-balanced mappings of
workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime
degradation. We first use this as the basis of a design space explorer that generates a variety
of configurations, trading off PE displacement vs. MTTF. Then, an efficient and optimized mixed LP and ILP (MILP)-based aging-aware floorplanner is proposed to increase
the MTTF without performance degradation. We also propose an integer linear programming (ILP)-based thermal-aware placement refinement algorithm that can be appended to any commercial placement and routing tool to decrease the maximum power density by an
order of magnitude and appreciably reduce the peak temperature of an ASIC.
Another aspect of hardware reliability is hardware obfuscation. The protection of intellectual
property (IP) has emerged as one of the most serious areas of concern in the semiconductor
industry. To address this issue, we present a method and architecture to map selective
portions of a design, given as a behavioral description for high-level synthesis (HLS) to a
high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only
the end-user has access to the full functionality of the chip. In all cases, the Time-ToBreak (T T B) is so long (at least 8 million hours) that for all practical purposes the designs
are secure, while incurring area overheads of around 5%
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
A MEMS-Assisted Dual-Resonator Temperature-to-Digital Converter
No full textMany applications demand precision oscillators, which are usually generated through employing resonators with high quality factor (Q). Quartz and MicroElectroMechanical systems (MEMS) are the most common precision resonators in today’s industry. Although quartz has been used in timing products for a long time, however, in the past couple of decades, MEMS resonators are gradually taking over a big portion of the market due to some advantages they have compared to quartz. With today’s resonator’s technology, precision oscillators require some types of compensation in order to achieve frequency stability of < ±1ppm over temperature. This work presents a high resolution temperature sensor employed in a MEMS-based programmable oscillator suitable for telecom applications. For the target application, the clock should have an Allan Deviation (ADEV) of < 1e−10 and frequency stability of < ±0.1ppm across the temperature range of −45˚C to 105˚C. Given the fact that in MEMS-based programmable oscillators the output clock is generated by a frequency synthesizer whose reference clock is made from the MEMS resonator, the frequency stability requirement necessitates utilization of a temperature sensor in order to apply a proper correction signal to the frequency synthesizer at each temperature. However, it must have enough resolution to ensure its noise does not violate the target output clock jitter. Also, it should have enough temperature tracking bandwidth to maintain frequency stability and ADEV in breezy conditions. This work presents a temperature-to-digital converter (TDC), designed in a 0.18µm CMOS process, based on a novel technique that achieves a resolution of 20µK over a bandwidth of 100Hz. By burning 19mW power, it gains an energy/resolution FOM of 0.04pJK2, showing around a 16x improvement on the previous state-of-the-art resolution FOM number among all the best temperature sensors reported so far. This TDC enabled us to successfully implement a MEMSbased programmable oscillator whose frequency stability and phase noise performance satisfy the telecom application requirements
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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