1,721,004 research outputs found
VeriIntel2C: Abstracting RTL to C to Maximize High-Level Synthesis Design Space Exploration
No full textDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).The design of integrated circuits (ICs) is typically done using low level Hardware Description Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full controllability of the generated hardware design as they allow to specify the detailed behaviour and structure of the architecture, at every single clock cycle. The main drawback of using these low level HDLs is that takes very long time to create and verify large ICs with them. Moreover, it is hard to re-use HDL code for future projects that require changes in the micro-architecture. Thus, the industry is moving the level of abstraction to C-based VLSI design where designers only have to specify the functionality of the program and High-Level Synthesis (HLS) tools generate the HDL automatically. One additional benefit of C-based VLSI design is that it enables to explore the search space of possible micro-architectures from a single behavioral description. The result of a Design Space Exploration (DSE) is a trade-off curve of Pareto-optimal designs with unique area vs. performance metrics. Most VLSI design companies have large amounts of legacy HDL code. Thus, it makes sense to have an automatic flow to convert HDL designs into behavioral descriptions (e.g. C, C++ or SystemC) optimized for HLS DSE. This implies that the generation of explorable constructs, e.g. loops and arrays, which upon exploration, lead to very different micro-architectures (e.g. loops can be unrolled or folded, arrays can be mapped to RAMs or registers). In this paper, we propose a robust RTL to C translation method called Verilntel2C to abstract RTL descriptions (written in Verilog) into ANSI-C descriptions optimized for HLS DSE by generating a large number of loops and arrays. Our method is able to generate these explorable constructs with the use of extended Hardware Petri Nets to extract the behaviour of the Verilog designs and to generate a Control Data Flow Graph (CDFG) that allows the easy identification of these constructs. From the experimental results, we are able to demonstrate that Verilntel2C expands the design space considerably and also improves the quality of design space by 55% on average compared to previous work, on a wide range of designs.Erik Jonsson School of Engineering and Computer Scienc
Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis
No full textDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).Commercial High-Level Synthesis (HLS) tool vendors have started to enable ways to protect Behavioral IP (BIPs) from being unlawful used. The main approach is to provide tools to encrypt these BIPs which can be decrypted by the HLS tool only. The main problem with this approach is that encrypting the IP does not allow BIP users to insert synthesis directives into the source code in the form of pragmas (comments), and hence cancels out one of the most important advantages of C-based VLSI design: The ability to automatically generate micro-architectures with unique design metrics, e.g. area, power and performance. This work studies the impact to the search space when synthesis directives are not able to be inserted in to the encrypted IP source code while other options are still available to the BIP users (e.g. setting global synthesis options and limiting the number and type of functional units) and proposes a method that selectively controls the search space by encrypting different portions of the BIP. To achieve this goal we propose a fast heuristic based on divide and conquer method. Experimental results show that our proposed method works well compared to an exhaustive search that leads to the optimal solution. © 2019 EDAA.Erik Jonsson School of Engineering and Computer Scienc
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
A machine learning based hard fault recuperation model for approximate hardware accelerators
No full textFull text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.Erik Jonsson School of Engineering and Computer Scienc
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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