55 research outputs found
Numerically efficient modeling of CNT transistors with ballistic and non-ballistic effects for circuit simulation
No full textThis paper presents an efficient carbon nanotube (CNT) transistor modeling technique which is based on cubic spline approximation of the non-equilibrium mobile charge density. The approximation facilitates the solution of the selfconsistent voltage equation in a carbon nanotube so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and non-ballistic transport theories and experimental results
Diagnosis of Multiple-Voltage Design with Bridge Defect
No full textMultiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost
A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects
No full textRecent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE
Low-energy standby-sparing for hard real-time systems
No full textTime-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this work is an online energy management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumptio
Application of Analog Adaptive Filters for Dynamic Sensor Compensation
No full textThis paper investigates the application of analog adaptive techniques to the area of dynamic sensor compensation, of which there is little reported work in the literature. The case is illustrated by showing how the response of a load cell can be improved to speed up the process of measurement. The load cell is a sensor with an oscillatory output in which the measurand contributes to the response parameters. Thus, a compensation filter needs to track variation in measurand whereas a simple, fixed filter is only valid at one specific load value. To facilitate this investigation, computer models for the load cell and the adaptive compensation filter have been developed. To allow a practical implementation of the adaptive techniques, a novel piecewise linearization technique is proposed in order to vary a floating voltage-controlled resistor in a linear manner over a wide range. Simulation and practical results are presented, thus demonstrating the effectiveness of the proposed techniques
Synchronization Overhead in SOC Compressed Test
No full textTest data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-a-chip. This paper analyzes the sources of synchronization overhead and discusses the different trade-offs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case
Reliable state retention-based embedded processors through monitoring and recovery
No full textState retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in FPGA and further synthesized using 65-nm technology to quantify the cost in terms of area, latency and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multi bit errors for a wide range of fault rates
A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks
No full textTurbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, Look-Up- Table-Log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental Add Compare Select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of- the-art Maximum Logarithmic Bahl-Cocke-Jelinek-Raviv (Max- Log-BCJR) implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m
Modeling SWCNT bandgap and effective mass variation using a Monte Carlo approach
No full textSynthesizing single-walled carbon nanotubes (SWCNTs) with accurate structural control has been widely acknowledged as an exceedingly complex task culminating in the realization of CNT devices with uncertain electronic behavior. In this paper, we apply a statistical approach in predicting the SWCNT bandgap and effective mass variation for typical uncertainties associated with the geometrical structure. This is first carried out by proposing a simulation-efficient analytical model that evaluates the bandgap (Eg) of an isolated SWCNT with a specified diameter (d) and chirality (θ). Similarly, we develop an SWCNT effective mass model, which is applicable to CNTs of any chirality and diameters >1 nm. A Monte Carlo method is later adopted to simulate the bandgap and effective mass variation for a selection of structural parameter distributions. As a result, we establish analytical expressions that separately specify the bandgap and effective mass variability (Egσ, mσ*) with respect to the CNT mean diameter (dµ) and standard deviation (dσ). These expressions offer insight from a theoretical perspective on the optimization of diameter-related process parameters with the aim of suppressing bandgap and effective mass variatio
Energy managed reporting for wireless sensor networks
No full textIn this paper, we propose a technique to extend the network lifetime of a wireless sensor network, whereby each sensor node decides its individual network involvement based on its own energy resources and the information contained in each packet. The information content is ascertained through a system of rules describing prospective events in the sensed environment, and how important such events are. While the packets deemed most important are propagated by all sensor nodes, low importance packets are handled by only the nodes with high energy reserves. Results obtained from simulations depicting a wireless sensor network used to monitor pump temperature in an industrial environment have shown that a considerable increase in the network lifetime and network connectivity can be obtained. The results also show that when coupled with a form of energy harvesting, our technique can enable perpetual network operatio
- …
