1,721,108 research outputs found
A low power 1024-channels spike detector using latch-based ram for real-time brain silicon interfaces
No full textHigh-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm2, dissipating 3.6 μW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs
Low-Power Energy-Based Spike Detector ASIC for Implantable Multichannel BMIs
No full textAdvances in microtechnology have enabled an exponential increase in the number of neurons that can be simultaneously recorded. To meet high-channel count and implantability demands, emerging applications require new methods for local real-time processing to reduce the data to transmit. Nonlinear energy operators are widely used to distinguish neural spikes from background noise featuring a good tradeoff between hardware resources and accuracy. However, they require an additional smoothing filter, which affects both area occupation and power dissipation. In this paper, we investigate a spike detector, based on a series of two nonlinear energy operators, and a simple and adaptive threshold, based on a three-point median operator. We show that our proposal provides good accuracy compared to other energy-based detectors on a synthetic dataset at different noise levels. Based on the proposed technique, a 1024-channel neural signal processor was designed in a 28 nm TSMC CMOS process by using latch-based static random-access memory (SRAM), demonstrating a total power consumption of 1.4 μW/ch and a silicon area occupation of 230 μm2/ch. These features, together with a comparison with the state of the art, demonstrate that our proposal constitutes an alternative for the development of next-generation multichannel neural interfaces
CFPM: Run-time Configurable Floating-Point Multiplier
No full textApproximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios
Anticorpi antivirali in pazienti pediatrici con IDDM all'esordio: elevata risposta IgA contro i virus della parotite e Coxsackie B-3
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