1,721,031 research outputs found
A review of the use of electro-thermal simulations for the analysis of heterostructure FETs
No full textThis paper deals with using device-level numerical simulations for the investigation of the electro-thermal behavior of a GaAs-based
heterostructure FET. We show a way of dealing with the software/hardware limitations related with the huge disproportion between the
electrically active region and the volume relevant to heat outflow. We study very wide simplified structures to obtain guidelines for building
up a reduced grid and proper boundary conditions for the complete simulation of the electro-thermal behavior of the FET. As an
application example, we use this approach to simulate the military standard (MIL-STD) method for the measurement of the thermal
resistance of GaAs FETs, thus discussing its accuracy and limitations. We also show that in multi-finger structures a single channel temperature
such as that obtained by electrical thermal resistance extraction techniques cannot satisfactorily describe the FET’s thermal
behavior. Finally, we briefly dwell on a comparison between 2D and 3D simulations
High-electric field effects and degradation of AlGaAs/GaAs power HFETs: a numerical study
No full textThis work presents a numerical study of high-field degradation and reliability issues of AlGaAs/GaAs power HFETs. A commercial two-dimensional drift-diffusion tool is used to investigate electric-field distributions, the effects of electron capture at the device surface under hot-carrier conditions, and the impact of drain recess scaling on such effects. Wherever experimental data are available for direct comparison, a good match is observed with our simulations. The main results of this study are (1) a validation of the hypothesis that attributes the main high-field degradation effects to electron capture over the gate-drain access region, and (2) design indications pointing out to the possibility of a reverse correlation between the gate-drain breakdown voltage and the device hot-carrier reliability
Numerical analysis of the effect of grain size and defects on the performance of CIGS solar cells
No full textThis work shows two-dimensional numerical simulations aimed at providing indications for the development of optimized thin-film CIGS solar cells. The poly-crystalline nature of CIGS and the presence of defects and Cu-poor regions at the grain boundaries and at the CIGS surface are taken into account, together with the possible displacement of the p-n junction from the CdS/CIGS heterojunction
On the combined effects of window/buffer and buffer/absorber conduction-band offsets, buffer thickness and doping on thin-film solar cell performance
No full textIn this study we perform an extensive campaign of numerical simulations of thin-film solar cell structures aimed at investigating how the conduction band offsets at buffer/window (ΔBW) and buffer/absorber (ΔAB) heterojunctions and the thickness and doping of the buffer layer combine to affect the performance parameters (Jsc, Voc, FF and η). For the two scenarios of ideal (i.e., without traps) and non-ideal (with traps) buffer/absorber interface, we vary ΔAB and ΔBW in the range -0.5 eV to 0.5 eV, and analyze, for each combination, the physical mechanisms limiting the cell performance and the way to optimize it by choosing optimal buffer doping and thickness. We show that assuming ΔAB as the main indicator of the performance potential of a cell can be misleading because ΔBW can heavily influence performance, even when ΔAB is positive (conduction band higher in the buffer than in the absorber) and near to its theoretical optimal value (0.3eV). However, we also show that ΔAB 0. We verify our findings by simulating several examples of CIGS-based solar cells with different buffer layers (CdS, Zn1-xMgxO, In2S3, Zn(O,S)) taken from the literature; these comparisons confirm the validity of our results and suggest that the combination of ΔAB and ΔBW is the predominant factor in the design of high-efficiency solar cells. We finally propose simple quantitative guidelines for thin-film solar cell design and optimization
Impact of Bulk and Interface Recombination on Wide-Bandgap CGS Solar Cells: Numerical Analysis of CdS and ZTO Buffer Layers
No full textSimulations were conducted to investigate the effects of bulk and interface recombination on the photovoltaic performance of a wide-bandgap CuGaSe2 (CGS) solar cell featuring a standard n-side stack of ZnO:Al/i-ZnO/CdS. The impact of replacing the CdS buffer layer with Zn1-xSnxO (ZTO) was tested for two different Sn compositions, revealing that the optimal composition is Zn0.8Sn0.2O. The performance of CGS solar cells employing the alternative ZTO buffer layer was found to improve compared to that of cells utilizing the traditional CdS buffer layer, under identical conditions of bulk carrier lifetimes in CGS and recombination rates at the buffer/absorber interface
Surface effects on turn-off characteristics of AlGaAs/GaAs HFETs
No full textThe gate-lag turn-off transient of as-fabricated and hut-carrier stressed power AlGaAs/GaAs NFETs is addressed by quantitatively comparing experimental data with device simulations accounting for the occupation dynamics of surface deep-acceptor trays. Gate-lag waveforms of increasingly degraded devices can be accurately simulated by suitably increasing the surface trap density
A software tool for thermal simulation and rating evaluation of high power silicon devices
No full textTemperature-dependent breakdown and hot carrier stress of PHEMTs
No full textThe main issues this work addresses, with reference to commercial GaAs PHEMTs, are the temperature dependence of the off-state breakdown voltage (BVDG), the physical mechanisms that determine it, and the relationship between BVDG and device degradation and failure, as determined by accelerated step-stress performed at temperatures ranging from 25 to 100°C. BVDG is seen to decrease with temperature between room temperature and 160°C. Temperature-dependent analysis of the gate leakage current indicates that thermionic-field emission and thermionic emission over a field-dependent barrier are the limiting mechanisms for off-state breakdown. Room-temperature, hot carrier step-stress tests with 24 h step duration show reduced IDSS after the stress and a tight correlation between the BVDG measured at IG = - 1 mA/mm and the stress bias producing substantial device degradation or catastrophic failure. Shorter (2 h) step stress experiments carried out between 25 and 100°C again show a tight correlation between the BVDG measured at IG = - 1 mA/mm and the stress bias producing dramatic degradation or failure. This correlation, coupled with the negligible temperature dependence of the breakdown voltage in this temperature range, results in temperature-independent device degradation
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