1,720,960 research outputs found
HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures
No full textDesign and test of a novel programmable clock generator semi-custom core for energy-efficient systems-on-chips
No full textCycle-accurate performance investigation of parallel Jpeg2000 on a multi-processor System-on-Chip platform
No full textSoftware Optimization of the JPEG2000 Algorithm on a VLIW CPU Core for System-on-Chip Implementation
No full textCircuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique
No full textThis work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications
A physical-level LCD driver model and simulator with application to pixel crosstalk suppression
No full textThe capability of early visual performance evaluation of alternative driving schemes is a major issue for time-effective and low-cost design of driver circuits for liquid crystal displays (LCD). We implemented a platform-independent, high-level, fully-configurable LCD driver simulation environment. The software incorporates an accurate driver/LC circuit model for reliable frequency characterization of the display module behavior. We demonstrated its efficiency in elaborating an optimal driving configuration that yields crosstalk-free image representation. The tool has been integrated into industrial design flows
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores
No full textSystem-on-chip market relies on implementing multimedia products as embedded software modules on re-usable architecture platforms. The efficient implementation of the Jpeg2000 encoder engine is still challenging HW and SW developers with its highly complex computational kernel. While several hardwired Jpeg2000 enconding modules exist, the efficient programming of Jpeg2000 on re-usable embedded high-performance cores is still an open issue. We performed an exhaustive analysis of the attainable execution speedup when specialized SW is run on different architectures built upon a multimedia-oriented VLIW processor core, demonstrating that the compression effort can be reduced by more than 50% if a SIMD-extended architecture is adopted, and by 80% when the code is optimized for a multi-core architecture
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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