1,721,211 research outputs found
A multi-folded MCML for ultra-low-voltage high-performance in deeply scaled CMOS
No full textIn this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation. The approach has been validated with post-layout simulations considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. In particular, OR/NOR gates with 3, 4, and 5 inputs implemented both with the conventional 2-inputs MCML gates implementation (Fin2) and the proposed MF MCML have been compared. Results show a reduction in the power consumption of the MF MCML equal to 3/4, 2/3 and 5/8 for the OR3, OR4 and OR5 logic functions respectively. Moreover, in terms of speed the Fin2 implementation has a delay at least 1.4 worst than the MF MCML, but is generally 1.7 worst than the proposed MF MCML gate. In this paper we have presented a novel approach which allows to implement MCML gates with a fan-in higher than 2 while keeping the minimum supply voltage as low as the one of a conventional MCML inverter. The proposed methodology, named Multi Folded MCML, born out by a generalization of the Folded MCML previously proposed by authors. The approach has been compared against the conventional Fin2 implementation (suited to implement arbitrarily logic function with a low power supply) both in terms of power consumption and propagation delay. The results have clearly demonstrated the advantages provided by the MF MCML. In particular, OR/NOR gates with 3-, 4-, and 5-inputs have been compared considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. Post layout simulation results have shown that the MF gates outperform the conventional implementations in terms of propagation delay for all the considered logic functions. In particular, the propagation delay of the Fin2 implementation has been shown to be at least 1.4 times higher than the one of the MF MCML implementation and even 2 times higher for other logic functions. The power consumption of the MF gates has been shown to be 3/4, 2/3 and 5/8 than the one of the Fin2 implementations for the OR3, OR4 and OR5 logic functions respectively. Hence, the only drawback of the propose techniques seems due to a more complex design procedure
The DD-Cell: a Double Side Entropic Source exploitable as PUF and TRNG
No full textIn this work we demonstrate that the DD-cell, previously proposed by the authors to implement weak PUFs, can behave also as a TRNG, thus allowing the implementation of PUF and TRNG primitives based on the same entropy source. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA device, and both PUF and TRNG functions have been verified through an extensive measurement campaign involving PVT variations. Measurements results have shown that the entropy of a DD-cell can reach a value higher than 0.99 without requiring any post-processing
A novel FPGA implementation of the NAND-PUF with minimal resource usage and high reliability
No full textIn this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
“Optimization of coarse synchronisation performances by non-linear signal pre-processing of GNSS signals in RADAR jammed environments”
No full textApproccio multidisciplinare per lo sviluppo di un modello di pesca responsabile nella Sicilia Nord orientale: il ruolo della piccola pesca artigianale
No full textAcute subarachnoid haemorrhage: 3D time-of-flight MR angiography versus intra-arterial digital angiography
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