91 research outputs found
Dithering-based real-time control of cascaded silicon photonic devices by means of non-invasive detectors
No full textReal-time control of multiple cascaded devices is a key requirement for the development of complex silicon photonic circuits performing new sophisticated optical functionalities. This article describes how the dithering technique can be leveraged in combination with non-invasive light probes to independently control the working point of many photonic components. The standard technique is extended by introducing the concept of orthogonal dithering signals to simultaneously discriminate the effect of different actuators, while the idea of frequency re-use is discussed to limit the complexity of control systems in cascaded architectures. After a careful analysis of the problem, the article presents an automated feedback strategy to tune and lock photonic devices in the maxima/minima of their transfer functions with given response speed and sensitivity. The trade-offs of this approach are discussed in detail to provide guidelines for the design of the feedback loop. Experimental demonstrations on a mesh of Mach-Zehnder interferometers and on cascaded ring resonators are discussed to validate the proposed control architecture in different scenarios and applications
Pitris, Marie (Birth, 1910-09-19)
No full textAddress: S W Cor Vine Liberty6044/1910Original record filed in drawer labeled 'PIERCE-PLAPP'
Automated Thermal Drift Compensation in WDM-based Silicon Photonic Multi-Socket Interconnect Systems
No full textWe present an on-chip AWGR-based interconnect system with automated thermal drift compensation along cascaded resonant structures in a dual-socket layout. Error-free operation in a 30 Gb/s data-routing scenario within a 12 °C temperature range is demonstrated
Φωτονική πυριτίου για δρομολόγηση και μετάδοση σε WDM αρχιτεκτονικές οπτικής διασύνδεσης επεξεργαστών
No full textThe last decade was dominated by the exponential growth of data, which are processed in Datacenters (DCs) and put DCs under enormous interconnection and computational strain. Optical interconnects enabled by Silicon (Si)-photonics have already penetrated into all levels of DC hierarchy to increase the bandwidth (BW) and latency limitations, targeting even to enable powerful optically-interconnected multi-socket boards for improved computational density and low power consumption (PC). This thesis contributed with the development of high-speed (≥40 Gb/s) wavelength division multiplexing (WDM) Si-photonic transceiver (TxRx) and passive routing devices for O-band and their incorporation in WDM Chip-to-Chip (C2C) Arrayed Waveguide Grating Router (AWGR)-based optical MSB architectures for high-performance computers. A cyclic-frequency 8×8 Si-photonic AWGR was developed for O-band featuring a coarse-WDM (CWDM) channel spacing of 10 nm. Its characterization revealed proper cyclic operation with channel losses between 2.5-6.05 dB (non-uniformity=3.55 dB) and a channel crosstalk (XT) of 11 dB. The AWGR was deployed in 25 Gb/s data routing experiments. A novel XT-aware transmission scheme with transmissions at detuned wavelengths was proposed to enable fully-loaded moderate-XT AWGR setups by addressing the in-band XT limitations and it was experimentally validated with the 8×8 Si-AWGR. A 4- and an 8-channel version of O-band high-speed WDM ring-modulator (RM)-based TxRxs were developed in Si-photonics and were successfully tested. The TxRxs relied on RMs for energy-, -size and bandwidth-related advantages and were the first with 160 Gb/s and 400 Gb/s Tx capabilities among all WDM Si- Txs, relying on high-speed line rate rather than on increased number of lanes or advanced modulation formats. A high-speed AWGR-based C2C optical MSB interconnection was proposed for the first time in O-band significantly exceeding the data rate from all previously reported counterparts in C-band. The interconnect was experimentally validated with recently-developed high-speed and energy-efficient TxRx and AWGR circuitry: i.e. an Si-RM as Tx, an Indium Phosphide photodiode co-packaged with a trans-impedance amplifier as Rx and the 8×8 Si-AWGR. The evaluation included 8 different data-routing scenarios with 8×25 Gb/s and 8×40 Gb/s signals representing data routing between processors. An analysis of the proposed architecture versus the dominant Intel’s QuickPath Interconnect (QPI) revealed significant energy savings (ES) of up to 69% in the Tx-Rx link energy efficiency (EE) in conjunction with improved system’s scalability and total MSB BW capacity. Finally, a “broadcast-friendly” (BF) version of the C2C AWGR-based optical MSB interconnection was proposed to efficiently handle the broadcast traffic in MSB, i.e. cache coherency updates. The BF architecture relied on the deployment of a universal Mach-Zehnder modulator (MZM) and its driver (DR) in the Tx layout so as to efficiently handle broadcasting and reducing, at the same time, the energy consumption (EC) associated with the simultaneous operation of all RMs. The scheme was experimentally validated by utilizing an integrated O-band Si-MZM as Tx and the 8×8 Si-AWGR for routing demonstrating simultaneous WDM transmission of 2×25 Gb/s signals. An analysis of the BF architecture link EE revealed additional improvements of 7% versus the initial architecture, translating to 76% ES compared to the EE of QPI.Η τελευταία δεκαετία καθορίστηκε από την εκθετική αύξηση των δεδομένων τα οποία επεξεργάζονται σε Κέντρα Δεδομένων (ΚΔ) και ασκούν τεράστια πίεση, υπολογιστικά και επικοινωνιακά. Οι οπτικές διασυνδέσεις πυριτίου έχουν εισχωρήσει σε όλα τα επίπεδα διασύνδεσης των ΚΔ με στόχο την αύξηση του εύρους ζώνης και τη μείωση της καθυστέρησης, στοχεύοντας ακόμα και σε εφαρμογές οπτικά-διασυνδεδεμένων πλακετών πολύ-επεξεργαστικών συστημάτων (MSBs) αυξημένης υπολογιστικής ισχύος και χαμηλής κατανάλωσης ενέργειας. Η παρούσα διατριβή συνείσφερε με την ανάπτυξη οπτικών πομποδεκτών υπερ-υψηλών ταχυτήτων (≥40 Gb/s) πολυπλεξίας μήκους κύματος (WDM) και παθητικών δρομολογητών βασισμένων σε φράγματα συστοιχίας κυματοδηγών (AWGR) για λειτουργία στην O-μπάντα και την ενσωμάτωσή τους σε αρχιτεκτονικές MSBs πλινθίου-σε-πλινθίο (C2C) με σκοπό την αντιμετώπιση των περιορισμών των ηλεκτρικών διασυνδέσεων σε υπολογιστικά συστήματα υψηλής απόδοσης. Αναπτύχθηκε ένας 8×8 παθητικός δρομολογητής πυριτίου AWGR για λειτουργία στην Ο-μπάντα, ο οποίος σχεδιάστηκε με αραιή (CWDM) απόσταση καναλιών 10 nm. Ο χαρακτηρισμός επέδειξε σωστή λειτουργία κυκλικής συχνότητας με απώλειες καναλιών μεταξύ 2.5-6.05 dB (μη ομοιομορφία=3.55 dB) και συνακρόαση (XT) 11 dB. Ο δρομολογητής χρησιμοποιήθηκε σε πειράματα δρομολόγησης δεδομένων 25 Gb/s. Προτάθηκε μια νέα τεχνική μετάδοσης σημάτων σε αποσυντονισμένα μήκη κύματος για την αντιμετώπιση του περιορισμού λόγω ενδοζωνικής παρεμβολής σε πλήρως-διασυνδεδεμένα συστήματα AWGR με μη-βέλτιστη συνακρόαση και επικυρώθηκε πειραματικά χρησιμοποιώντας τον 8×8 AWGR. Αναπτύχθηκαν δύο WDM οπτικοί πομποδέκτες πυριτίου 4- και 8-καναλιών αντίστοιχα, για λειτουργία στην Ο-μπάντα. Οι πομποδέκτες βασίστηκαν σε διαμορφωτές δακτυλίου (RM) για χαμηλή κατανάλωσης ενέργειας, μικρό μέγεθος και υψηλό εύρος ζώνης και ήταν οι πρώτοι παγκοσμίως με δυνατότητες πομπού 160 Gb/s και 400 Gb/s μεταξύ των WDM πομπών πυριτίου, βασιζόμενοι σε υψίρυθμα κανάλια και σε όχι αυξημένο αριθμό καναλιών είτε διαμόρφωσης ανώτερης τάξης. Σε επίπεδο αρχιτεκτονικής, προτάθηκε μια C2C οπτική διασύνδεση AWGR για MSBs στην Ο-μπάντα υπερβαίνοντας σημαντικά τον ρυθμό δεδομένων σε σχέση με όλες τις AWGR-διασυνδέσεις για MSBs οι οποίες και έχουν επιδειχθεί στη C-μπάντα. Η διασύνδεση επικυρώθηκε πειραματικά με προσφάτως-ανεπτυγμένα υψίρυθμα και ενεργειακώς- αποδοτικά φωτονικά κυκλώματα στην Ο-μπάντα: έναν διαμορφωτή δακτυλίου πυριτίου ως πομπό, μία φωτοδίοδο τεχνολογίας φωσφιδίου του ινδίου με ενισχυτή διαντίστασης (ΤΙΑ) ως δέκτη και τον 8×8 AWGR. Η αξιολόγηση περιελάμβανε 8 σενάρια δρομολόγησης με σήματα 8×25 Gb/s και 8×40 Gb/s που αντιπροσώπευαν δρομολόγηση δεδομένων μεταξύ επεξεργαστών. Η προτεινόμενη αρχιτεκτονική δύναται να προσφέρει έως και 69% καλύτερη ενεργειακή απόδοση στην οπτική ζεύξη έναντι της κυρίαρχης Intel QPI, το οποίο έρχεται σε συνδυασμό με υψηλή κλιμάκωσης και συνολικό εύρος ζώνης. Τέλος, προτάθηκε μια “φιλική ως-προς-την-πολλαπλή-εκπομπή” εκδοχή της C2C AWGR-οπτικής διασύνδεσης με σκοπό να διαχειρίζεται ενεργειακώς-αποδοτικά τις πολλαπλές εκπομπές στις MSBs, πχ. μηνύματα συνοχής cache. Η βελτιωμένη αρχιτεκτονική βασίστηκε στην ενσωμάτωση ενός επιπλέον διαμορφωτή Mach-Zehnder (ΜΖΜ) στους πομπούς στοχεύοντας στη μείωση της κατανάλωση ενέργειας από τους ΔΔ κατά τις πολλαπλές εκπομπές. Η αρχιτεκτονική επικυρώθηκε πειραματικά με τη χρήση ενός διαμορφωτή πυριτίου MZM ως πομπού και του 8×8 AWGR σε ταυτόχρονη WDM μετάδοση δύο σημάτων 2×25 Gb/s, υποσχόμενη βελτιώσεις έως κατά 7% στην ενεργειακή απόδοσης της ζεύξης σε σχέση με την αρχική αρχιτεκτονική πομπών διαμορφωτών δακτυλίου οδηγώντας σε 76% βελτίωση σε σύγκριση με το Intel QPI
Phase Imaging Microscopy: Beyond Dark-Field, Phase Contrast, and Differential Interference Contrast Microscopy
No full textFirst demonstration of an optical content addressable memory (CAM) cell at 10 Gb/s
No full textWe experimentally demonstrate the first all-optical Content Addressable Memory (CAM) cell, employing a monolithically integrated InP Flip-Flop and a SOA-MZI XOR gate. Error-free operation during Write operation and Content Addressing is achieved at 10 Gb/s.</p
Breast Micro-Calcifications Dataset with Precisely Annotated Sequential Mammograms
No full text<p><strong>Breast Micro-Calcifications Dataset with Precisely Annotated Sequential Mammograms</strong></p>
<p><strong>Citing the Dataset</strong></p>
<p>The dataset is released under a Creative Commons Attribution license, so please cite the dataset if it is used in your work in any form. Published academic papers should use the academic paper citation for our paper. Personal works, such as projects or blog posts, should provide a URL to this Zenodo page, though a reference to our paper would also be appreciated.</p>
<p><em>Academic paper citation</em></p>
<p>Loizidou, K., Skouroumouni, G., Pitris, C. <em>et al.</em> Digital subtraction of temporally sequential mammograms for improved detection and classification of microcalcifications. <em>Eur Radiol Exp</em> <strong>5, </strong>40 (2021). https://doi.org/10.1186/s41747-021-00238-w</p>
<p><em>Personal use citation</em></p>
<p>Include a link to this Zenodo page - 10.5281/zenodo.5036062</p>
<p><strong>ACKNOWLEDGMENT</strong></p>
<p>This research is funded by the European Union’s Horizon 2020 research and innovation program under grant agreement No. 739551 (KIOS CoE) and from the Republic of Cyprus through the Directorate General for European Programs, Coordination and Development.</p>
<p><strong>Contact Information</strong></p>
<p>If you would like further information about the dataset, or if you experience any issues downloading files, please contact us at [email protected].</p>
<p><strong>General Information</strong></p>
<p>This dataset consists of 100 pairs of mammograms, from two temporally sequential rounds. Specifically, this dataset includes the prior and recent mammograms of CC and MLO view of each patient. This is a complete dataset for the detection and BI-RADS classification of breast micro-calcifications, using digital mammograms. It contains normal (BI-RADS 1), benign (BI-RADS 2), and suspicious (BI-RADS 4-5) cases, and for each mammogram, an image with precise annotation of each individual micro-calcification, by two expert radiologists, is provided. In 32 suspicious cases, the biopsy results are also available.</p>
<p><strong>More details are available in the README.txt</strong></p>Another dataset related only to breast masses can be accessed here: 10.5281/zenodo.7179856
Breast Masses Dataset with Precisely Annotated Sequential Mammogram
WDM-Enabled Optical RAM at 5 Gb/s Using a Monolithic InP Flip-Flop Chip
No full textArt. 0600207, 8 S.We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance.8Nr.
An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s
No full textWe propose and experimentally demonstrate the first all-optical content addressable memory (CAM) cell that comprises an all-optical monolithically integrated InP flip-flop and an optical XOR gate. The experimental results reveal error-free operation at 10 Gb/s for both content addressing and content writing operations. The potential of these memory architectures to allow for up to 40-Gb/s operation could presumably lead to fast CAM-based routing applications by enabling all-optical address look-up schemes.</p
WDM-Enabled Optical RAM at 5 Gb/s Using a Monolithic InP Flip-Flop Chip
No full textWe experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6 × 2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance.</p
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