512 research outputs found
Enhancement of Transistor-to-Transistor Variability Due to Total Dose Effects in 65-nm MOSFETs
No full textWe studied device-to-device variations as a function of total dose in MOSFETs, using specially designed test structures and procedures aimed at maximizing matching between transistors. Degradation in nMOSFETs is less severe than in pMOSFETs and does not show any clear increase in sample-to-sample variability due to the exposure. At doses smaller than 1 Mrad( SiO 2 ) variability in pMOSFETs is also practically unaffected, whereas at very high doses-in excess of tens of Mrad( SiO 2 )-variability in the on-current is enhanced in a way not correlated to pre-rad variability. The phenomenon is likely due to the impact of random dopant fluctuations on total ionizing dose effects
1GigaRad TID impact on 28nm HEP analog circuits
No full textThe Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response
1GigaRad TID impact on 28 nm HEP analog circuits
No full textAn in-depth analysis of modern technologies could represent the base for the success of the High Luminosity Large Hadron Collider experiments. The requirement is a new reliable electronics in 1Grad-TID environments. For the purpose, single devices in TSMC 28 nm bulk CMOS technology have been realized and studied. Preliminary experimental results demonstrate nMOS structures more resistant than pMOS. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as the pixel readout channel hereby presented. In the particular case, the high radiation level induces a gain reduction and a slowdown of the time response
Novel Imaging Sensor for High Rate and High Resolution Applications
No full textSquare CCD and CMOS arrays are commonly employed to perform two-dimensional imaging tasks as they offer high image quality and spatial resolution. For more specific applications, where the requirement is to locate the position of a fast moving, single luminous spot over a delimited area (single particle positioning, beam spot monitoring, ...) such kind of devices is somewhat cumbersome to use, due to the huge number of pixels needed to be read in order to get high resolution the spatial position of the luminous signal. The data throughput limits the use of pixel arrays to those applications where a time resolution of a few hundred frames per second is sufficient. In this contribution we propose a novel device, based on solid state sensors, able to perform two dimensional imaging of a luminous spot with a frame rate (first prototype) of about 10 kHz and a spatial resolution better than 800*800 points over a 25mm diameter circular field of view. A full performance characterization of the first prototype is also reported
A 110 nm CMOS process for fully-depleted pixel sensors
No full textThis work presents a customized 110 nm CMOS process on high-resistivity substrate tailored for the production of fully-depleted pixel sensors. Starting from n-type substrates, customized surface implantations have been introduced to enable fast and efficient collection of the charge generated by ionizing particles or radiation. Double-sided processing has been used to define the backside electrode and the termination structures needed to bias the sensors at high voltage. A first run showing the feasibility of 300 μm-thick fully-depleted sensors was completed, and several test devices designed for the assessment of the process were fabricated together with a 24 × 24 pixels array with 50 μm pitch. The main technological challenges and the customization of the process are discussed, and electrical measurements on test devices demonstrating the functionality of the termination structures, the full depletion of the substrate and the fast charge collection are presented
Monolithic pixel sensors in deep-submicron SOI technology with analog and digital pixels
No full textInvestigation of leakage current and breakdown voltage in irradiated double-sided 3D silicon sensors
No full textWe report on an experimental study aimed at gaining deeper insight into the leakage current and breakdown voltage of irradiated double-sided 3D silicon sensors from FBK, so as to improve both the design and the fabrication technology for use at future hadron colliders such as the High Luminosity LHC. Several 3D diode samples of different technologies and layout are considered, as well as several irradiations with different particle types. While the leakage current follows the expected linear trend with radiation fluence, the breakdown voltage is found to depend on both the bulk damage and the surface damage, and its values can vary significantly with sensor geometry and process details
Drain Current Collapse in 65 nm pMOS Transistors After Exposure to Grad Dose
No full textTotal ionizing dose (TID) response of pMOS transistors featuring a commercial 65 nm CMOS technology was studied by X-ray irradiation up to 1 Grad (SiO2), which emulated total dose target in the LHC upgrade. After irradiation, dramatic reduction of drain current was observed, the degradation level showed a strong dependency on gate width. At total doses higher than 208 Mrad(SiO2), the off-state leakage was heightened by more than one order of magnitude, which was attributed to the gate-induced drain leakage (GIDL) due to the positive charge trapping in STI and/or gate oxide. The subthreshold swing (SS) and the threshold voltage remained practical constant even at 1 Grad (SiO2) total dose. The degradation in the drain current can be partially explained by the radiation induced narrow channel effect due to the positive charge trapping in STI. However, from the comparison results under two bias conditions during irradiation, there must be other mechanisms contributing together. Damage of the gate oxide could be another mechanism contributing to the dramatic drain current reduction
Investigation of Supply Current Spikes in Flash Memories Using Ion-Electron Emission Microscopy
No full textWe studied the occurrence of supply current spikes and destructive events in NAND flash memories under heavy-ion exposure. In addition to broad-beam experiments, we used collimated beams and ion-electron emission microscopy to investigate the phenomena on two types of memories with different feature size. Current spikes on the supply current were observed in both devices, also with collimated beams, whereas destructive events occurred only with broad beam. We show that current spikes do not originate from charge-pump capacitors, as previously suggested, and propose that destructive events are due to the effects of temporally close heavy-ion hits on distinct areas of the tested chips
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