38 research outputs found

    Effect of co-administration of different doses of phenylephrine with oxytocin on the prevention of oxytocin-induced hypotension in caesarean section under spinal anaesthesia: A randomised comparative study

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    Introduction: Co-administration of phenylephrine prevents oxytocin-induced hypotension during caesarean section under spinal anaesthesia (SA), but higher doses cause reflex bradycardia. This study compares the effects of co-administration of two different doses of phenylephrine on oxytocin-induced hypotension during caesarean section under SA. Methods: In this prospective, double-blind study, 90 parturients belonging to the American Society of Anesthesiologists' physical status 1 or 2, undergoing caesarean section under SA were randomised into Group A: oxytocin 3U and phenylephrine 50 μg, Group B: oxytocin 3U and phenylephrine 75 μg, Group C: oxytocin 3U and normal saline, administered intravenously over 5 min after baby extraction. The incidence of hypotension (the primary outcome), rescue vasopressor requirement and side effects were recorded. Statistical analyses were with analysis of variance, Kruskal-Wallis, chi-square and Fisher's exact tests. Results: Demographic parameters such as age, height, weight, level of sensory block at 20 min and duration of surgery were comparable in all the groups. The incidence of hypotension (Group A – 90%, Group B – 10%, Group C – 98%, P = 0.001), magnitude of fall in mean arterial pressure (Group A-15.03 ± 6.12 mm of Hg, Group B – 6.63 ± 4.49 mm of Hg and Group C-13.03 ± 3.39 mm of Hg, P < 0.001) and rescue vasopressor requirement (Group A-45 ± 15.25 mg, Group B-5 ± 15.25, Group C-91.66 ± 26.53, P < 0.001) were significantly lower in Group B compared to A and C. Conclusion: Co-administration of phenylephrine 75 μg with oxytocin 3U reduces the incidence of oxytocin-induced hypotension compared to phenylephrine 50 μg with oxytocin 3U during caesarean section under spinal anaesthesia

    Structure factor of interacting one-dimensional helical systems

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    peer reviewedWe calculate the dynamical structure factor S(q,ω)S(q,\omega) of a weakly interacting helical edge state in the presence of a magnetic field BB. The latter opens a gap of width 2B2B in the single-particle spectrum, which becomes strongly nonlinear near the Dirac point. For chemical potentials μ>B|\mu|>B, the system then behaves as a nonlinear helical Luttinger liquid, and a mobile-impurity analysis reveals power-law singularities in S(q,ω)S(q,\omega) which depend on the interaction strength as well as on the spin texture of the edge states. For μ<B|\mu|<B, the low-energy excitations are gapped, and we determine S(q,ω)S(q,\omega) by using an analogy to exciton physics

    Top-Down Integration Methodology for Clocking Blocks into High Speed Serial IO

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    High Speed Serial Input-Output (HSIOs) design architecture is widely used for many applications in today’s System-On-Chips (SOCs). SOCs integrate a number of protocols including PCIe, SATA, SD4, USB3, etc. which are based on IO architecture. Typical HSIO integrates Analog blocks such as Receiver (Rx), Transmitter (Tx) and Clocking (PLL, Clock Distribution) functions along with sea of logic gates for PCS (Physical Connectivity Sub layer), logic micro-partitions for Tx/Rx power management, encoding/decoding and Serialization/Deserialization functions. The top level design database is typically RTL leading to a sea of gates when synthesized. The top level design is implemented using standard ASIC design flow including RTL, Simulation, Synthesis, Timing, Place & Route, and Formal Verification etc. However, the partitions for Tx, Rx, PLL and Clocking are Analog/Custom hard-macros. To ensure proper functionality, integrity (for low power, timing, Place and route, Mixed Signal/IP level validation) we need to model hard-macros in a digital friendly manner. For functionality verification purpose, we model the macro behavior in Verilog, timing needs to be abstracted in industry standard liberty file format (lib file), for place and route we abstract the physical information in LEF/FRAM format etc. In HIP, while there are methods to build these individually, streamlined methodology for building these with consistency, quality and flow friendly manner is missing. The focus of this project is to formulate a methodology for hard-macro integration into top level HSIO database, and apply this for Secure Digital card (SD4) IO that is being developed in IP Blocks. DOI: 10.17762/ijritcc2321-8169.15066

    Challenges in Modelling and Verification of Transmitter Circuits for Advanced Mobile Storage Physical layer

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    Abstract: Flash memory is a key component of today’s mobile phones providing embedded storage for text and media and removable storage for a variety of purposes e.g. Video. Many standard bodies support mobile storage e.g. sdcard.org, Universal flash storage org. Mobile storage today is evolving continuously with ever increasing bandwidth and capacity demands. IP Blocks and Technologies Groups specializes in providing Host controller and Physical Layer solution for variety of mobile devices including phones, tablets, laptops/ultra-books Current project is focusing on Physical layer design and verification – which consists of Digital Frontend (DFE) including Serial/De-serializer, encoding, decoding schemes, and an analog front-end (AFE) which consists of Transmitter/Receiver Circuits. The Phy also includes PLL, Clock Distribution and Compensation circuits to support DFE and AFE. The focus of the current project is to develop methodology and techniques to validate transmitter circuit for mobile storage comprehensively. DOI: 10.17762/ijritcc2321-8169.15066

    A Comprehensive Survey on Resource Management in Internet of Things

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    Efficient resource management is a challenging task in distributed systems, such as the Internet of Things, fog, edge, and cloud computing. In this work, we present a broad overview of the Internet of Things ecosystem and of the challenges related to managing its resources. We also investigate the need for efficient resource management and the guidelines given/suggested by Standard Development Organizations. Additionally, this paper contains a comprehensive survey of the individual phases of resource management processes, focusing on resource modeling, resource discovery, resource estimation, and resource allocation approaches based on performance parameters or metrics, as well as on architecture types. This paper presents also the architecture of a generic resource management enabler. Furthermore, we present open issues concerning resource management, pointing out the directions of future research related to the Internet of Things

    A Comprehensive Survey on Resource Management in Internet of Things, Journal of Telecommunications and Information Technology, 2020, nr 4

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    Efficient resource management is a challenging task in distributed systems, such as the Internet of Things, fog, edge, and cloud computing. In this work, we present a broad overview of the Internet of Things ecosystem and of the challenges related to managing its resources. We also investigate the need for efficient resource management and the guidelines given/suggested by Standard Development Organizations. Additionally, this paper contains a comprehensive survey of the individual phases of resource management processes, focusing on resource modeling, resource discovery, resource estimation, and resource allocation approaches based on performance parameters or metrics, as well as on architecture types. This paper presents also the architecture of a generic resource management enabler. Furthermore, we present open issues concerning resource management, pointing out the directions of future research related to the Internet of Thing

    feed forward FFT architecture

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    Electric-field-induced Majorana Fermions in Armchair Carbon Nanotubes

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    We consider theoretically an armchair carbon nanotube (CNT) in the presence of an electric field and in contact with an s-wave superconductor. We show that the proximity effect opens up superconducting gaps in the CNT of different strengths for the exterior and interior branches of the two Dirac points. For strong proximity induced superconductivity the interior gap can be of the p-wave type, while the exterior gap can be tuned by the electric field to be of the s-wave type. Such a setup supports a single Majorana bound state at each end of the CNT. In the case of a weak proximity induced superconductivity, the gaps in both branches are of the p-wave type. However, the temperature can be chosen in such a way that the smallest gap is effectively closed. Using renormalization group techniques we show that the Majorana bound states exist even after taking into account electron-electron interactions

    Effects of Internal Heat Generation and Variable Viscosity on Onset of Rayleigh-Benard Convection

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    In the present study, onset of stationary Rayleigh-Benard convective instability in a fluid layer, with internal heating and thermally dependent viscosity has been investigated by means of linear stability analysis. The dependence of viscosity is assumed to be exponential. The resulting eigen value problem is solved using a regular perturbation technique with wave number a as a perturbation parameter. The viscosity parameter and the presence of internal heat source play a decisive role on the stability characteristics of the system. It is observed that both stabilizing and destabilizing factors can be enhanced because of the simultaneous presence of a volumetric heat source and variable viscosity so that a more precise control (suppress or augment) of thermal convective instability in a fluid layer is possible.</jats:p
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