215 research outputs found
RNS support for RSA cryptography
No full textThe majority of currently established public-key cryptosystems, e.g., RSA, ECC, requires modular multiplication in finite fields as their core operation. As a result, the throughput rate of such cryptosystem depends upon the speed of modular multiplication and upon the number of performed modular multiplications. Montgomery algorithm is one method that allows efficient implementation of multiplication modulo large number, as required by the RSA cryptosystem. In the recent years, renewed interest has been payed to Residue Number Systems (RNS), due to their ability to enable parallel and fast modular arithmetic. Within RNS any integer is represented with a set of its residues with respect to a given base that comprises a set of relatively prime integers. In this way RNS distributes large dynamic range computations over small modular rings. Thus the computations are carried out independently in each of the small wordwidth RNS channels. Since the RNS is particularly suited for performing efficient long integer modular arithmetic, the Montgomery algorithm was adapted such that it can be utilized in conjunction with RNS. RNS Montgomery modular multiplication makes use of two representation bases B and B', and during the calculations requires two base extension operations. Such a base extension involve the calculation of the residue digits with respect to , when the digits relative to are known, and dominates the RNS Montgomery modular multiplication computational complexity. This thesis evaluates existing base extensions methods and proposes a new improved approach, which makes use of the linear Diophantine equations theory. Assuming that and are -moduli sets, to derive the value of new residues, our method requires regular multiplications and modular multiplications, while equivalent state-of-the-art methods require, depending on the extension sense, to or to , and modular multiplications, respectively. When utilized in the RSA context, our method provides a speedup of relative to the stateof-the art, where is the ratio between the computation time required by a modular multiplication and by a regular one. To better asses the practical implications of the proposed method we implemented RSA based on state of the art and on the Diophantine theory and compared their performance. For the evaluations we assumed various RSA keysizes, , different RNS moduli sets with varying cardinality (=4, 5, and 6), bitlength and Hamming weight, and various messages to encrypt. Our experimental results indicate that for sets of 4, 5, and 6 moduli with bitlength of 512-bits, our method provides a speedup per Montgomery kernel of 1.93, 2.42, and 3.17, respectively.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Cost Effective Modular Adders for RNS-based Processors
No full textRNS can distribute the computation on long operands over small word-width RNS functional units able to operate in parallel. This property is the ground to develop fast arithmetic units. While RNS can boost addition and multiplication performance, other arithmetic operations like division, magnitude comparison, and sign detection are more difficult, when compared with their counterparts in the conventional binary number system. In view of that RNS is mostly utilized for special-purpose applications, e.g., digital filters, which are addition and multiplication dominated. For such applications the RNS capability to represent large numbers and the carry-free nature of arithmetic operations are of interest and can potentially enable fast and low-power arithmetic computation. The overall performance of any RNS based processor is mostly determined by the selected moduli set and the way the modular operations, i.e., addition and multiplication, are implemented in hardware (note that this two issues are intertwined). In this thesis we concentrate on the design of fast and energy effective modular adders able to compute |A + B|_m = (A + B if A + B < m, if otherwise A + B - m) as they are the fundamental building block for any RNS processor. We base our solution on a state of the art approach, i.e., ELM Modular Addition (ELMMA), which utilize anticipated computation in conjunction with fast parallel prefix addition. Our method follows the same anticipation principle but reduces the overall complexity by proposing an alternative design for the adders, which can now directly handle three inputs instead of two. In this way the initial carry-save addition required for ELMMA for the evaluation of the A+B-m is not longer required and this may potentially result in faster and more area and power effective designs. To evaluate the impact of our proposal we considered a number of moduli of practical interest as follows: 2^n - (2^{n-2} + 1), 2^n - 2^{n-2}, and 2^n - (2^{n-3}+1). For the considered moduli we implemented in VHDL two sets of implementations, i.e., one for the state of the art ELMMA and one for our proposal, for the n=16 case. We simulated, debug, and synthesized the designs using Cadence Encounter RTL Compiler for ASIC Designs for 90 nm CMOS technology. Our results indicate that for moduli 2^n - (2^{n-2} + 1), 2^n-2^{n-2}, and 2^n-(2^{n-3}+1), our proposal requires 13%, 32%, and 28% smaller area, is 14%, 3%, and 9% faster, and is 15%, 20%, and 13% more power efficient, respectively, when compared with the state of the art.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
An Efficient VLSI Architecture for Matrix Based RNS Backward Converter
No full textAbstractResidue Number System (RNS) is the important research area from last five decades. Forward & backward conversion process is the bottle neck which limits the use of RNS for computing needs. In this paper, we proposed an efficient VLSI architecture for Matrix based RNS backward converter. We analysed the performance of proposed architecture for different modulo sets of size up to ten . Implemented using TSMC standard cell 180nm CMOS technology libraries and result analysis indicated that, the performance of proposed converter achieved about 59% area reduction and 30% efficient with respective to Time-Delay Product when compared to the state of art Backward converters
RNS-Based NTT Polynomial Multiplier for Lattice-Based Cryptography
No full textabstract: Lattice-based Cryptography is an up and coming field of cryptography that utilizes the difficulty of lattice problems to design lattice-based cryptosystems that are resistant to quantum attacks and applicable to Fully Homomorphic Encryption schemes (FHE). In this thesis, the parallelization of the Residue Number System (RNS) and algorithmic efficiency of the Number Theoretic Transform (NTT) are combined to tackle the most significant bottleneck of polynomial ring multiplication with the hardware design of an optimized RNS-based NTT polynomial multiplier. The design utilizes Negative Wrapped Convolution, the NTT, RNS Montgomery reduction with Bajard and Shenoy extensions, and optimized modular 32-bit channel arithmetic for nine RNS channels to accomplish an RNS polynomial multiplication. In addition to a full software implementation of the whole system, a pipelined and optimized RNS-based NTT unit with 4 RNS butterflies is implemented on the Xilinx Artix-7 FPGA(xc7a200tlffg1156-2L) for size and delay estimates. The hardware implementation achieves an operating frequency of 47.043 MHz and utilizes 13239 LUT's, 4010 FF's, and 330 DSP blocks, allowing for multiple simultaneously operating NTT units depending on FGPA size constraints.Dissertation/ThesisMasters Thesis Electrical Engineering 202
VHDL Implementation of 4096-bit RNS Montgomery Modular Exponentiation for RSA Encryption
No full textModular exponentiation is the basis needed to perform RSA encryption and decryption. Execution of 4096-bit modular exponentiation using an embedded system requires many arithmetic operations. This work aims to improve the performance of modular exponentiation for an existing FPGA platform containing a soft core RISC-V processor. The solution is to introduce a peripheral that performs Montgomery multiplication with 4096-bit operands. These operands are represented using the Residue Number System (RNS) and each residue is assigned to a RNS processor core. In total, the system consists of 121 RNS cores and each core is responsible for a 34-bit residue. RNS Montgomery multiplication requires a base extension algorithm, which will be represented by the Bajard and the Shenoy base extensions. Two designs are proposed: one using a tree-based reduction circuit and one with an iterative reduction circuit. The former focuses on performance overall, while the latter is more efficient in terms of performance per area. Synthesis for a XCKU035 FPGA gives an area usage of 83484 LUTs for the tree-based design and 41857 LUTs for the iterative design. Both designs also require 132.5 BRAMs and 485 DSP blocks and are running at a clock frequency of 400 MHz. The tree-based design performs Montgomery multiplication using 4096-bit operands in 434 cycles (1.09 µs), while the iterative design does that in 577 cycles (1.44 µs). For performing modular exponentiation, the sliding window method is used with an optimal window size of seven. A modular exponentiation with 4096-bit operands takes on average 5.09 ms for the tree-based design, while the iterative version needs 6.78 ms. Few other implementations were found performing Montgomery multiplication using 4096-bit operands. However, compared to those the proposed design provides better performance.Computer Engineerin
A New RNS 4-moduli Set for the Implementation of FIR Filters
No full textabstract: Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The critical aspect in the application of RNS is the selection of the moduli set and the design of the conversion units. There have been several RNS moduli sets proposed for the implementation of digital filters. However, some are unbalanced and some do not provide the required dynamic range. This thesis addresses the drawbacks of existing RNS moduli sets and proposes a new moduli set for efficient implementation of FIR filters. An efficient VLSI implementation model has been derived for the design of a reverse converter from RNS to the conventional two's complement representation. This model facilitates the realization of a reverse converter for better performance with less hardware complexity when compared with the reverse converter designs of the existing balanced 4-moduli sets. Experimental results comparing multiply and accumulate units using RNS that are implemented using the proposed four-moduli set with the state-of-the-art balanced four-moduli sets, show large improvements in area (46%) and power (43%) reduction for various dynamic ranges. RNS FIR filters using the proposed moduli-set and existing balanced 4-moduli set are implemented in RTL and compared for chip area and power and observed 20% improvements. This thesis also presents threshold logic implementation of the reverse converter.Dissertation/ThesisM.S. Electrical Engineering 201
Functional Type Assignment for Featherweight Java - To Rinus Plasmeijer, in Honour of His 61st Birthday.
Get PDF23.06.14 KB. Ok to add the accepted version to spiral. Embargo still in place until 4 Sep 1
Survey Results of the New Health Care Worker Study: Implications of Changing Employment Patterns
Get PDFThis report examines the effects of contemporary employment arrangements on the quality of nursing work life, and the implications of these employment arrangements for individual nurses, the hospitals, and also for the organization. First we look at nurse work status (full-time, part-time or casual job), contract status (permanent or temporary), and employment preference as factors affecting commitment to the hospital and profession, job satisfaction, retention in the organization, and absenteeism from work. Second, we examine stress, burnout, and physical occupational health problems (in particular, musculoskeletal disorders), as affecting nurse and hospital outcomes. This project investigated how the quality of nursing worklife and career choices differ for nurses in full-time, part-time and casual employment, and whether nurses who have the employment arrangements they prefer enjoy a standard of worklife that encourages retention. We collected data for the study from 1,396 nurses employed at three large teaching hospitals in Southern Ontario (Hamilton Health Sciences, Kingston General Hospital, and St. Michael's Hospital in Toronto) using the New Health Care Worker Questionnaire. Results indicate that although a substantial majority of the nurses were employed in the type of job that they preferred, problems of stress, burnout and physical health problems were reported. Further, these problems affected the nurses' job satisfaction, commitment, and propensity to leave the hospitals.health care workers, employment status, nurses, job satisfaction, commitment, stress, burnout, physical health problems, MSD, propensity to leave
Retirement decision-making among registered nurses’ and allied health professionals: A descriptive analysis of Canadian longitudinal study on aging data
No full textA population’s health is dependent on the availability of skilled health professionals. We
know little about retirement decision-making among publicly employed Canadian registered
nurses (RNs) and allied health professionals (AHPs). We identified and compared factors
reported to influence early versus 65+ retirement decisions among RNs (n = 794) and AHPs
(n = 393). RNs, on average, retired at 58.1 years and AHPs at 59.4 years. More than two
thirds retired before age 65. Among RNs, caregiving demands predict early retirement –
policies supportin
Table 1. Commentators for special sleep and dreams issue
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