1,722,038 research outputs found
Compact modelling in RF CMOS technology
Get PDFWith the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work
RF CMOS Class C Power . . .
No full textRF CMOS Class C Power Amplifiers for Wireless Communications by Ramakrishna Sekhar Narayanaswami Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Abstract 2 order in order to generate an approximate solution to the design goal before a circuit analysis tool is required. Circuit techniques used to combat the technology limitations imposed by CMOS technologies include the use of differential circuits in the signal path, cascoded stages and a modified tuning method which allowed for the use of extremely large output devices but not requiring passive devices that were not feasible in a CMOS technology
Analysis, Design and Optimization of RF CMOS Polyphase Filters
No full textDie Dissertation erscheint parallel im<a
href="http://www.shaker-online.com">
Shaker-Verlag, Aachen. - ISBN 3-8322-4542-1
Polyphase filters (PPFs) are an efficient solution for high accuracy quadrature generation in radio frequency (RF) CMOS design. Although there are some guidelines for design of RF CMOS PPFs, they give too much freedom. With layout considerations, optimization of RF CMOS PPFs cannot be reached by using analytical calculations because of many constraints and tradeoffs in the design. Thus, in design of RF CMOS PPFs, intensive trials and several design iterations are needed to reach given specifications. In this situation, a computer-aided analysis and design optimization tool for RF CMOS PPFs is of great help to the community of RF CMOS PPFs designers, especially for industrial projects that are under time-to-market pressures. However, such a dedicated tool has not been available until now, to the authors best knowledge. Focusing on computer-aided analysis and design optimization tools for RF CMOS PPFs, this dissertation has the following scientific contributions:
PPFANA, a dedicated computer-aided software tool for analysis of the influences from the nonideal effects, namely, process tolerance, components mismatch on the quadrature accuracy of the RF CMOS PPFs, was developed by the author and presented in this dissertation.
Physical design considerations for RF CMOS PPFs in system-on-a-chip (SoC) solution were proposed by the author through the analysis on the influences from parasitic effects in RF SoC.
Silicon success of an RF CMOS PPF designed by the author for a low-IF Bluetooth receiver using Fraunhofer-IMS 0.6 µm CMOS process was achieved.
PPFOPTIMA, a computer-aided synthesis and optimization tool for RF CMOS PPFs with dedicated worst-case simulation and Monte Carlo simulation toolboxes for verification of the performance of RF CMOS PPFs, was developed by the author and presented in this dissertation
Analysis, design and optimization of RF CMOS polyphase filters
No full textPolyphase filters (PPFs) are an efficient solution for high accuracy quadrature generation in radio frequency (RF) CMOS design. Although there are some guidelines for design of RF CMOS PPFs, they give too much freedom. With layout considerations, optimization of RF CMOS PPFs cannot be reached by using analytical calculations because of many constraints and tradeoffs in the design. Thus, in design of RF CMOS PPFs, intensive trials and several design iterations are needed to reach given specifications. In this situation, a computer-aided analysis and design optimization tool for RF CMOS PPFs is of great help to the community of RF CMOS PPFs designers, especially for industrial projects that are under time-to-market pressures. However, such a dedicated tool has not been available until now, to the author's best knowledge. Focusing on computer-aided analysis and design optimization tools for RF CMOS PPFs, this dissertation has the following scientific contributions: PPFANA, a dedicated computer-aided software tool for analysis of the influences from the nonideal effects, namely, process tolerance, components mismatch on the quadrature accuracy of the RF CMOS PPFs, was developed by the author and presented in this dissertation. Physical design considerations for RF CMOS PPFs in system-on-a-chip (SoC) solution were proposed by the author through the analysis on the influences from parasitic effects in RF SoC. Silicon success of an RF CMOS PPF designed by the author for a low-IF Bluetooth receiver using Fraunhofer-IMS 0.6 µm CMOS process was achieved. PPFOPTIMA, a computer-aided synthesis and optimization tool for RF CMOS PPFs with dedicated worst-case simulation and Monte Carlo simulation toolboxes for verification of the performance of RF CMOS PPFs, was developed by the author and presented in this dissertation
An integrated optical receiver in MS/RF CMOS process
No full textA monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance
Reliability engineering in RF CMOS
Get PDFIn this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies
MS／RF CMOS工艺兼容的光电探测器
No full text为实现光纤通信系统中的单片光电集成，采用工业标准工艺设计了硅基光电探测器，讨论了光电探测器的机理，提出了五种新的探测器结构，并采用TSMC0．18μmMS／RF CMOS工艺进行了流片．利用半导体测试仪对芯片进行了测试，包括探测器的暗电流、响应度和结电容，并分析了深n阱、浅沟槽隔离等工艺步骤对探测器参数的影响．结果表明，利用标准MS／RF CMOS工艺实现的光电探测器具有良好的特性
MS/RF CMOS工艺兼容的光电探测器模拟与测试
No full text设计了一种新型的与MS/RF CMOS工艺全兼容、带深n阱(DNW)、浅沟槽隔离(STI)的双光电探测器,分析了其工作机理,用器件模拟软件ATLAS对其暗电流、响应电流、光调制频率响应和波长响应进行了模拟.采用TSMC 0.18 μm MS/RF CMOS工艺进行了流片,对芯片进行了暗电流和响应度的测试.模拟和测试结果均表明,该探测器与常规双光电探测器相比,具有较低的暗电流和较高的响应度
RF CMOS reliability simulations
Get PDFWe present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process
RF CMOS-MEMS cantilever resonator
No full textThis paper presents use of the simple cantilever
beam as RF CMOS-MEMS resonator, which can be scaled like
transistor with improved performance. This resonator can be
used in the oscillator and filter part of RF transceiver, which can
actually be fabricated on chip without losing its Q-factor. The
cantilever beam resonator was designed using COMSOL4.3b™
and produce resonance frequency at 10.2MHz, pull-in voltage at
1.5V and Q of 10000
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