170,623 research outputs found
Coarse-grained reconfiguration: dataflow-based power management
Full text linkPower reduction in modern embedded systems design is a challenging issue exacerbated by the complexity and heterogeneity of their architecture. In the field of Reconfigurable Video Coding (RVC), to challenge these issues and cut-down time to market, dataflow-based techniques have been adopted. In particular, to master management and composability of dynamically reconfigurable systems, the authors have developed the multi-dataflow composer. Nevertheless, despite the RVC offers several different tools, in its reference design framework power management is still an open issue. To make some steps forward towards filling this gap, in this study, they address power management for coarse-grained reconfigurable systems combining structural and dynamic strategies, both to be applied at the dataflow level. © The Institution of Engineering and Technology 2015
DSE and profiling of multi-context coarse-grained reconfigurable systems
No full textThe implementation of multi-context systems over coarse-grained reconfigurable platforms could bring several benefits in terms of efficient resource usage and power management. Nevertheless on-the-fly reconfiguration and mapping are not so straightforward and the optimal configuration of the substrate could be extremely time consuming. In this paper we present an early stage design space exploration methodology intended for dataflow-based design flows where multiple input specifications have to be taken into account. The proposed approach, coupled to the Multi-Dataflow Composer tool, has been exploited to assemble the central reconfigurable computing core of an accelerator for video/image processing
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy
No full textApplications and hardware complexity management in modern systems tend to collide with efficient resource and power balance. Therefore, dedicated and power-aware design frameworks are necessary to implement efficient multi-functional runtime reconfigurable signal processing platforms. In this work, we adopt dataflow specifications as a starting point to challenge power minimization
Carta della biodiversità vegetale e crittogamica delle aree forestali di Pizzo Manolfo, Crocetta Trippatore e Raffo Rosso
No full textCarta di sintesi della biodiversità vegetale e crittogamica delle aree forestali di Pizzo Manolfo, Crocetta Trippatore e Raffo Rosso (Palermo) correlata a dati climatici ed ecologic
A Custom dual-processor System for Real-time Neural Signal Processing
No full textThis paper presents a custom dual-processor SoC architecture, studied and customized to support information extraction from signals acquired from Peripheral Neural System, for prosthetic applications. The main tasks accomplished by the processing implemented on the computing platform are noise removal and identification of neural spikes. On-board execution of such tasks allows to identify which samples actually contain useful information. Thus, it reduces required input/output bandwidth, so that connection to the external environment can be implemented using a Bluetooth Low Energy device. The overall SoC architecture has power consumption compliant with implant-related constraints with a battery lifetime of around one-day. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved
Sentir-pensando. Liana Borghi: una bio-bibliografia in fieri
No full textRicostruzione cronologica della produzione teorica e dell'attivismo politico di Liana Borghi, dal 1976 al 2021
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
Full text linkModern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches. This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with
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