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Analysis and design of low-power data converters
Full text linkIn a large number of applications the signal processing is done exploiting both
analog and digital signal processing techniques. In the past digital and analog
circuits were made on separate chip in order to limit the interference and other
side effects, but the actual trend is to realize the whole elaboration chain on a
single System on Chip (SoC). This choice is driven by different reasons such as the
reduction of power consumption, less silicon area occupation on the chip and also
reliability and repeatability. Commonly a large area in a SoC is occupied by digital
circuits, then, usually a CMOS short-channel technological processes optimized to
realize digital circuits is chosen to maximize the performance of the Digital Signal
Proccessor (DSP). Opposite, the short-channel technology nodes do not represent
the best choice for analog circuits. But in a large number of applications, the signals
which are treated have analog nature (microphone, speaker, antenna, accelerometers,
biopotential, etc.), then the input and output interfaces of the processing chip are
analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC)
both digital and analog circuits can be found. This gives advantages in term of total
size, cost and power consumption of the SoC. The specific characteristics of CMOS
short-channel processes such as:
• Low breakdown voltage (BV) gives a power supply limit (about 1.2 V).
• High threshold voltage VTH (compared with the available voltage supply) fixed
in order to limit the leakage power consumption in digital applications (of the
order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many
problems with the stacked topologies.
• Threshold voltage dependent on the channel length VTH = f(L) (short channel
effects).
• Low value of the output resistance of the MOS (r0) and gm limited by speed
saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20
to 26dB.
• Mismatch which brings offset effects on analog circuits.
make the design of high performance analog circuits very difficult. Realizing lowpower
circuits is fundamental in different contexts, and for different reasons: lowering
the power dissipation gives the capability to reduce the batteries size in mobile
devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the
life of remote sensing devices, satellites, space probes, also allows the reduction of
the size and weight of the heat sink. The reduction of power dissipation allows the
realization of implantable biomedical devices that do not damage biological tissue.
For this reason, the analysis and design of low power and high precision analog
circuits is important in order to obtain high performance in technological processes
that are not optimized for such applications. Different ways can be taken to reduce
the effect of the problems related to the technology:
• Circuital level: a circuit-level intervention is possible to solve a specific problem
of the circuit (i.e. Techniques for bandwidth expansion, increase the gain,
power reduction, etc.).
• Digital calibration: it is the highest level to intervene, and generally going to
correct the non-ideal structure through a digital processing, these aims are
based on models of specific errors of the structure.
• Definition of new paradigms.
This work has focused the attention on a very useful mixed-signal circuit: the
pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in
high-precision applications where a resolution of about 10-16 bits and sampling
rates above hundreds of Mega-samples per second (telecommunication, radar, etc.)
are needed. An introduction on the theory of pipeline ADC, its state of the art
and the principal non-idealities that affect the energy efficiency and the accuracy
of this kind of data converters are reported in Chapter 1. Special consideration is
put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep
submicron technology nodes side effects called short channel effects exist opposed to
older technology nodes where undesired effects are not present. An overview of the
short channel effects and their consequences on design, and also power consuption
reduction techniques, with particular emphasis on the specific techniques adopted
in pipelined ADC are reported in Chapter 2. Moreover, another way may be
undertaken to increase the accuracy and the efficiency of an ADC, this way is the
digital calibration. In Chapter 3 an overview on digital calibration techniques, and
furthermore a new calibration technique based on Volterra kernels are reported. In
some specific applications, such as software defined radios or micropower sensor,
some circuits should be reconfigurable to be suitable for different radio standard
or process signals with different charateristics. One of this building blocks is the
ADC that should be able to reconfigure the resolution and conversion frequency. A
reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply
starting from the required conversion frequency was developed, and the results are
reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for
the feedback loop and its theory is described
Calibration of pipeline ADC with pruned Volterra kernels
Full text linkA Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1-2.5 bits (6-15 dB) with 37101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques
Calibrating sample and hold stages with pruned Volterra kernels
No full textSwitched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10-24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out-of- sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB
A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier
No full textA novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like the conventional common-drain voltage follower, it has class-A behavior. Class-AB behavior enables faster settling with large capacitive loads and/or lower power consumption
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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