186,256 research outputs found
Thermal-Safe Test Scheduling for Core-Based System-on-a-Chip Integrated Circuits
No full textOverheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC) integrated circuits. Several power-constrained test scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the non-uniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test scheduling approach that is able to produce short test schedules and guarantee thermal-safety at the same time. Two thermal-safe test scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test scheduling algorithm may not be feasible. Based on a low-complexity test session thermal cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm
Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction
No full textPower dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum transition don't care fill, special scan cells and scan chain partitioning), very little work has been carried out towards reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex ATPG algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2-3%). An algorithmic procedure for assigning flip-flips to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and respectively maximum number of simultaneous transitions
Thermal-aware SoC test scheduling with test set partitioning and interleaving
No full textHigh temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach
Rapid generation of thermal-safe test schedules
No full textOverheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have been recently proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test
Minimizing Test Power in SRAM through Reduction of Pre-charge Activity
No full textIn this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations
Analysing trade-offs in scan power and test data compression for Systems-on-a-chip
No full textThis paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data
The Nash Equilibrium requires strong cooperation
No full textContrary to the customary view that the celebrated Nash-equilibrium theorem in Game Theory is paradigmatic for non-cooperative games, it is shown that, in fact, it is essentially based on a particularly strong cooperation assumption. Furthermore, in practice, this cooperation assumption is simply unrealistic.non-cooperation, strong cooperation, mixup in the Nash equilibrium
Author-wise bibliometric analysis based on entropy.
No full textAuthor-wise bibliometric analysis based on entropy.</p
Performability/energy trade-off in error-control schemes for on-chip networks
No full textHigh reliability against noise, high performance, and low energy consumption are key objectives in the design of on-chip networks. Recently some researchers have considered the impact of various error-control schemes on these objectives and on the trade-off between them. In all these works performance and reliability are measured separately. However, we will argue in this paper that the use of error-control schemes in on-chip networks results in degradable systems, hence performance and reliability must be measured jointly using a unified measure, i.e., performability. Based on the traditional concept of performability, we provide a definition for the 'Interconnect Performability'. Analytical models are developed for interconnect performability and expected energy consumption. A detailed comparative analysis of the error-control schemes using the performability analytical models and SPICE simulations is provided taking into consideration voltage swing variations (used to reduce interconnect energy consumption) and variations in wire length. Furthermore, the impact of noise power and time constraint on the effectiveness of error-control schemes are analyze
SystemC-based Minimum Intrusive Fault Injection Technique with Improved Fault Representation
No full textIn this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved
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