1,720,976 research outputs found
Modelling, Simulation and Characterization of Tunnel-FET Devices for Ultra-low Power Electronics
Full text linkIn the last years a significant effort has been spent by the microelectronic industry to reduce the chip power consumption of the electronic systems since the latter is becoming a major
limitation to CMOS technology scaling.
Many strategies can be adopted to reduce the power consumption. They range from the system to the electron device level. In the last years Tunnel Field Effect Transistors (TFET) have imposed as possible candidate devices for replacing the convential MOSFET in ultra low
power application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-Band Tunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptive revolutionary device concept.
This thesis investigates TFET modeling and simulation, a very challenging topic because of the difficulties in modeling BtBT accurately. We present a modified Multi Subband Monte Carlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB) Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implemented with arbitrary semiconductor materials. The model accounts for carrier quantization with a heuristic but accurate quantum correction validated by means of comparison with full quantum model and experimental results.
The MSMC model has been used to simulate and assess the performance of idealized homo- and hetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds.
In the second part of the thesis we discuss the characterization of TFETs at low temperature. Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble, France) are considered with the objective to identify the possible presence of alternative injec-
tion mechanisms such as Trap Assisted Tunneling
Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel
No full textThis paper reports a simulation study investigating
the drive current of a prototypical SiGe n-type FinFET built
on a relaxed SiGe substrate for different values of the Ge
content x in the Si(1−x)Gex active layer. To this purpose, we
performed strain simulations, band-structure calculations, and
multisubband Monte Carlo transport simulations accounting for
the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering
Calibrated multi-subband Monte Carlo modeling of tunnel-FETs in silicon and III–V channel materials
No full textWe present a semiclassical model for Tunnel-FET (TFET) devices capable to describe band-to-band tunneling
(BtBT) as well as far from equilibrium transport of the generated carriers. BtBT generation is implemented
as an add-on into an existing multi-subband Monte Carlo (MSMC) transport simulator that
accounts as well for the effects typical to alternative channel materials and high-j dielectrics. A simple
but accurate correction for the calculation of the BtBT generation rate to account for carrier confinement
in the subbands is proposed and verified by comparison with full 2D quantum calculation
Multi-Subband Semi-classical Simulation of n-type Tunnel-FETs
No full textWe present a newly developed model for Tunnel-
FET (TFET) devices capable to describe band-toband
tunneling (BtBT) as well as off-equilibrium
transport of the generated carriers. BtBT generation
is implemented as an add-on into an existing
Multi-subband Monte Carlo (MSMC) transport
simulator that accounts for the effects of alternative
channel materials and high- dielectrics. A simple
correction for the calculation of the BtBT generation
rate is proposed to account for carrier confinement
in the subbands
Device variability and correlation control by automated tuning of SPICE cards to PCM measurements
No full textWe present an improved methodology to calibrate nominal SPICE models to individual or average PCM measurements at the die, wafer or lot level. The method overcomes previous difficulties in the structured handling of huge amounts of PCM data and it is validated in a state-of-the-art mixed-signal system-on-chip product development environment for the 65 nm CMOS technology node. The proposed approach is especially useful for real time process control to tackle model-hardware correlation problems in a multi-foundry design environment, to ease the burden of transferring designs to new production sites and to complement common tools available to the designers to cope with process variability such as worst-case corner models and Monte Carlo simulations
On the Optimization of SiGe and III-V Compound Hetero-Junction Tunnel FET Devices
No full textWe investigate the operation and performance of planar SiGe/Si and n0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET
(TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the heterojunction and the metallurgical junction is beneficial to improve
ION but for the considered devices the ON-current at VDD=0.5V and IOFF=1pA/m hardly exceeds 1A/m. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems
High Performance SiGe Nanowire Tunnel FETs: Low Temperature Characterization for Device Process Optimization
No full textThis paper presents SiGe nanowire tunneling field effect transistors (TFETs) cointegrated with MOSFETs. The process is detailed, and the differences between TFET injection (Band-to-Band Tunneling or BTBT) and MOSFET thermionic injection are outlined. The fabricated TFETs exhibit record ON-current performances at room temperature, three times higher than previous state of the art. Low-temperature measurements are conducted to clarify the device physics. It is shown that subthreshold slope degradation is a result of trap assisted tunneling; careful control of the defect-inducing process steps could lead to slopes lower than 60mV/dec at room temperature, without degradation of ON-state current
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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