1,720,957 research outputs found
Dataset for 'Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS'
No full textThis dataset supports the article entitled "Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS"
accepted for publication in IEEE Journal of Solid State Circuits, October 2018</span
Dataset supporting the journal article "Pragmatic Memory-System Support for Intermittent Computing using Emerging Non-Volatile Memory"
No full textSivert T. Sliper, William Wang, Nikos Nikoleris, (2022) Pragmatic Memory-System Support for Intermittent
Computing using Emerging Non-Volatile Memory. (Accepted/In press) In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14 p
All files are in csv or ods format, both of which can be opened in spreadsheet programs like Libre Office Sheet or proprietary alternatives such as Microsoft Excel.</span
Evaluation and analysis of single-phase clock flip-flops for NTV applications
No full textPerformance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Celllevel design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted
Pragmatic memory-system support for intermittent computing using emerging non-volatile memory
No full textIntermittent computing (IC) is a key enabler for the vision of a trillion Internet of Things devices. By harvesting energy from the environment, and leveraging non-volatile memory (NVM) to retain computational progress across power cycles, IC enables untethered and battery-free devices to perform computation whenever ambient energy is available. The backbone of state retention is NVM, and recent advances in energy-efficient NVM have the potential to expand the application domain of IC significantly. Utilizing emerging NVM at the level of bitcells, researchers have proposed non-volatile processors. However, these do not leverage hardware-software co-design, which can be used to overcome hardware limitations and to provide support for application-level constraints such as atomicity. In this paper, we propose MEMIC, a memory architecture tailored for IC devices with byte-addressable NVM. A core focus of MEMIC is to combine volatile-and non-volatile memory in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule. MEMIC uses volatile memory for energy efficiency, and nonvolatile memory for data retention. To avoid double-buffered checkpoints and costly roll-backs when code needs to be reexecuted, MEMIC is designed to track and minimize writes to non-volatile memory during failure-atomic sections. Our evaluation shows that MEMIC&#x2019;s instruction cache reduces workload completion time under intermittent operation by 41-70% and its data cache provides a further reduction of 13-39%.</p
Ultra-low power 18-transistor fully-static contention-free single-phase clocked flip-flop in 65nm CMOS
No full textFlip-flops are essential building blocks of sequential digital circuits, but typically occupy a substantial proportion of chip area and consume significant amounts of power. This work proposes 18TSPC, a new topology of fully-static contention-free Single-Phase Clocked (SPC) Flip-Flop (FF) with only 18 transistors, the lowest number reported for this type. Implemented in 65nm CMOS, it achieves 20% cell area reduction compared to the conventional Transmission Gate FF (TGFF). Simulation results show the proposed 18TSPC is 3 times more efficient than TGFF in the Energy-Delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift-register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6V, 25ºC show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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