1,721,135 research outputs found
On-line testing of permanent radiation effects in reconfigurable systems
No full textCassano L, Cozzi D, Korf S, Hagemeyer J, Porrmann M, Sterpone L. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE; 2013: 717-720
Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture
No full textSterpone L, Sabena D, Ullah A, Porrmann M, Hagemeyer J, Ilstad J. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. IEEE; 2013: 184-188.The usage of reconfigurable systems is of increasingly interest for space and avionic applications. In the present work we propose an implementation flow for hardening Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results performed by heavy-ions radiation experiments and fault injection campaigns demonstrate the effectiveness of the proposed method
Realtime multiprocessor for mobile ad hoc networks
Full text linkJungeblut T, Grünewald M, Porrmann M, Rückert U. Realtime multiprocessor for mobile ad hoc networks. Advances in Radio Science. 2008;6:239-243.This paper introduces a real-time Multiprocessor
System-On-Chip (MPSoC) for low power wireless applications.
The multiprocessor is based on eight 32bit RISC processors
that are connected via an Network-On-Chip (NoC).
The NoC follows a novel approach with guaranteed bandwidth
to the application that meets hard realtime requirements.
At a clock frequency of 100MHz the total power consumption
of the MPSoC that has been fabricated in 180 nm
UMC standard cell technology is 772mW
A Reconfigurable SOM Hardware Accelerator
Full text linkPorrmann M, Franzmeier M, Kalte H, Witkowski U, Rückert U. A Reconfigurable SOM Hardware Accelerator.A dynamically reconfigurable hardware accelerator for self-organizing
feature maps is presented. The system is based on the universal rapid prototyping system RAPTOR2000 that has been developed by the authors. The modular prototyping system is based on XILINX FPGAs and is capable of emulating hardware implementations with a complexity of more than 24 million system
gates. RAPTOR2000 is linked to its host – a standard personal computer or
workstation – via the PCI bus. For the simulation of self-organizing maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex series and optionally up to 128 MBytes of SDRAM. A speedup of about 50 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing maps
Hardware Accelerators for Elliptic Curve Cryptography
Full text linkPuttmann C, Shokrollahi J, Porrmann M, Rückert U. Hardware Accelerators for Elliptic Curve Cryptography. Advances in Radio Science. 2008;6:259-264.In this paper we explore different hardware accelerators
for cryptography based on elliptic curves. Furthermore,
we present a hierarchical multiprocessor system-onchip
(MPSoC) platform that can be used for fast integration
and evaluation of novel hardware accelerators. In respect
of two application scenarios the hardware accelerators are
coupled at different hierarchy levels of the MPSoC platform.
The whole system is implemented in a state of the art 65 nm
standard cell technology. Moreover, an FPGA-based rapid
prototyping system for fast system verification is presented.
Finally, a metric to analyze the resource efficiency by means
of chip area, execution time and energy consumption is introduced
Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation
Full text linkLangen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze
the differences between a prototypical FPGA implementation and standard cell realizations
in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using
the hardware description language VHDL, which offers the opportunity of adding special, optimized
hardware blocks for various operations. The effects on area and power consumption as
well as computational power are analyzed. A detailed overview of the implementation of additional
hardware multipliers and their effects on the above mentioned topics concludes this paper
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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