5,351 research outputs found
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
No full textSterpone L, Porrmann M, Hagemeyer J. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers. 2013;62(8):1508-1525.Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory
Reconfiguration Viewer
Full text linkGrassi PR, Pohl C, Porrmann M. Reconfiguration Viewer. In: Design Automation and Test in Europe, DATE University Booth. Nice, France; 2009.The proposed approach allows debugging of partial dynamic reconfiguration. It shows where and when FPGA areas are reconfigured at runtime
On-line testing of permanent radiation effects in reconfigurable systems
No full textCassano L, Cozzi D, Korf S, Hagemeyer J, Porrmann M, Sterpone L. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE; 2013: 717-720
Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.
No full textDurelli G, Santambrogio MD, Cresci F, Porrmann M, Sciuto D. Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling. In: 19th Reconfigurable Architectures Workshop (RAW 2012). 2012
Contro la funzionalizzazione della contrattazione collettiva. Riflessioni sul pensiero di Mario Rusciano
No full textL'autore riflette sul pensiero di Mario Rusciano in punto di funzionalizzazione della contrattazione collettiva.The author reflects on the thought of Mario Rusciano in relation to the subject of the functionalisation of collective bargaining
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing
Full text linkPurnaprajna M, Pohl C, Porrmann M, Rückert U. Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, July 13-16, 2009, Las Vegas, Nevada, USA. 2009: 119-125.Parallelism and adaptability are two distinct architectural
design considerations in embedded processors. Multicore
processors accelerate application execution on account of
their inherent parallelism and run-time reconfiguration capabilities
add adaptability during infield deployment. To benefit from
both these features, a reconfigurable multiprocessor architectur
Realtime multiprocessor for mobile ad hoc networks
Full text linkJungeblut T, Grünewald M, Porrmann M, Rückert U. Realtime multiprocessor for mobile ad hoc networks. Advances in Radio Science. 2008;6:239-243.This paper introduces a real-time Multiprocessor
System-On-Chip (MPSoC) for low power wireless applications.
The multiprocessor is based on eight 32bit RISC processors
that are connected via an Network-On-Chip (NoC).
The NoC follows a novel approach with guaranteed bandwidth
to the application that meets hard realtime requirements.
At a clock frequency of 100MHz the total power consumption
of the MPSoC that has been fabricated in 180 nm
UMC standard cell technology is 772mW
Hardware Accelerators for Elliptic Curve Cryptography
Full text linkPuttmann C, Shokrollahi J, Porrmann M, Rückert U. Hardware Accelerators for Elliptic Curve Cryptography. Advances in Radio Science. 2008;6:259-264.In this paper we explore different hardware accelerators
for cryptography based on elliptic curves. Furthermore,
we present a hierarchical multiprocessor system-onchip
(MPSoC) platform that can be used for fast integration
and evaluation of novel hardware accelerators. In respect
of two application scenarios the hardware accelerators are
coupled at different hierarchy levels of the MPSoC platform.
The whole system is implemented in a state of the art 65 nm
standard cell technology. Moreover, an FPGA-based rapid
prototyping system for fast system verification is presented.
Finally, a metric to analyze the resource efficiency by means
of chip area, execution time and energy consumption is introduced
Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation.
No full textPorrmann M. Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation. Vol 104. Paderborn: HNI-Verlagsschriftenreihe, Heinz Nixdorf Institut, Schaltungstechnik; 2002
Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation
Full text linkLangen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze
the differences between a prototypical FPGA implementation and standard cell realizations
in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using
the hardware description language VHDL, which offers the opportunity of adding special, optimized
hardware blocks for various operations. The effects on area and power consumption as
well as computational power are analyzed. A detailed overview of the implementation of additional
hardware multipliers and their effects on the above mentioned topics concludes this paper
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