70,097 research outputs found
VLSI design of a pipelined CORDIC processor
No full textIn this report we discuss the VLSI realisation of a pipelined CORDIC arithmetic unit to perform stable matrix row operations for the solution of systems of linear equations. The algorithmic considerations of the CORDIC process are highlighted and a chip level architecture is derived from these to implement the algorithm in a pipelined manner. We then proceed to give details of the 2pm CMOS processor that has been designed to implement that architecture
Notes on the design of a barrel shifter for the Warwick pipelined CORDIC processor
No full textThis document discusses the design decisions made during the design of the barrel shifters used in the floating point adjustment circuitry of the Warwick pipelined CORDIC processor. The barrel shifter is required for both the input (mantissa alignment) and output (post normalistion) parts of the floating data path, although it also has applications in other areas such as a bit field extraction and multiplication/division. A brief survey of the available techniques will be given, followed by a discussion of the design process for the Barrel shifters in our implementatioof the CORDIC algorith
On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification
No full textMicroprocessor pipelining is a well-established technique that improves performance and reduces power consumption by overlapping instruction execution. Verifying, however, that an implementation meets this ISA specification is complex and time-consuming. One of the key verification issues that must be addressed is that of overlapping instruction execution. This can introduce hazards where, for instance, a new instruction reads the value from a register which will be written by an earlier instruction that has not yet completed. Using Event-B’s support for refinement with automated proof, a method is explored where the abstract machine represents directly an instruction from the ISA that specifies the effect that the instruction has on the microprocessor register file. Refinement is then used systematically to derive a concrete, pipelined execution of that instruction. Microarchitectural considerations are raised to the specification level and design choices can be verified much earlier in the flow. The method proposed therefore has the potential to be integrated into an existing high-level synthesis methodology, providing an automated design and verification flow from high-level specification to hardware
Methodology for the formal specification of RTL RISC processor designs (with particular reference to the ARM6)
No full textDue to the need to meet increasingly challenging objectives of increasing performance, reducing power consumption and reducing size, synchronous processor core designs have been increasing significantly in complexity for some time now. This applies to even those designs originally based on the RISC principle of reducing complexity in order to improve instruction throughput and the performance of the design.
As designs increase in complexity, the difficulty of describing what the design does and demonstrating that the design does indeed do this, also increases. The usual practice of describing designs using natural languages rather than formal language exacerbates this because of the ambiguities inherent in natural language descriptions. Hence this thesis is concerned with the development of a scalable methodology for the creation of a formal description of synchronous processor core design
Not only does the methodology of this thesis provide a standardised approach for describing synchronous processor core designs, but the description that it generates can be used as a basis for the formal verification of the solutions to the problem that increasing complexity poses for traditional validation.
The concept of different presentations of one description is part of the methodology of this thesis and is use to reconcile differences in how the description is best used for one purpose or another.
The methodology of this thesis was developed for the formal specification of the ARM6 processor core and thus this design provides the primary example used in this thesis. Case studies of the use of the methodology of this thesis with other processor cores and a modernised version of the ARM6 are also discussed
New virtually scaling free adaptive CORDIC rotator
No full textIn this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2
Automated Design of a Functionally
No full textAcknowledgments We are greatly indebted to our supervisors Prof. Anshul Kumar and Prof. M. Balakrishnan for their invaluable technical guidance and moral support during the course of the project. We are grateful to Satya Kiran, Basant Kumar Dwivedi and Anup Gangwar for their guidance and suggestions at various stages of the project. We would also like to thank the Embedded Systems Group for their co-operation. Last but not the least, we thank our batchmates who have motivated us all along. Also dedicated to the memory of laptop and chaibiscuit who have been subjects of many invigorating conversations and healthy leg-pullings. Varun Kodthivada Prashant Aggarwa
A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM
No full textIn this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 ?m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption
Bit-level pipelined digit-serial array processors
No full textA new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented
Author Co-Citation Analysis (ACA): a powerful tool for representing implicit knowledge of scholar knowledge workers
No full textIn the last decade, knowledge has emerged as one of the most important and valuable organizational assets. Gradually this importance caused to emergence of new discipline entitled ―knowledge management‖. However one of the major challenges of knowledge management is conversion implicit or tacit knowledge to explicit knowledge. Thus Making knowledge visible so that it can be better accessed, discussed, valued or generally managed is a long-standing objective in knowledge management. Accordingly in this paper author co- citation analysis (ACA) will be proposed as an efficient technique of knowledge visualization in academia (Scholar knowledge workers)
Accelerating software radio astronomy FX correlation with GPU and FPGA co-processors
No full textIncludes abstract.Includes bibliographical references (leaves [117]-121).This thesis attempts to accelerate compute intensive sections of a frequency domain radio astronomy correlator using dedicated co-processors. Two co-processor implementations were made independently with one using reconfigurable hardware (Xilinx Virtex 4LXlOO) and the other uses a graphics processor (Nvidia 9800GT). The objective of a radio astronomy correlator is to compute the complex valued correlation products for each baseline which can be used to reconstruct the sky's radio brightness distribution. Radio astronomy correlators have huge computation demands and this dissertation focuses on the computational aspects of correlation, concentrating on the X-engine stage of the correlator
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