1,720,967 research outputs found
Application specific instruction set processor for sensor conditioning in automotive applications
Full text linkIn the automotive electronic market, sensor conditioning is one of the driving applications. Sensor solutions are pervasive in the vehicle, while signal processing in such application is getting more and more complex. Currently the design strategy is often the standard ASIC flow, but the design effort can be reduced by automatic or platform-aided design strategies, or by using software-based solutions. In this paper SensASIP platform is presented. It is a design platform targeting a microprocessor architecture enhanced by dedicated instructions for computing intensive sensor signal processing tasks. SensASIP allows a seamless design flow from MATLAB-based algorithm definition and instruction set design and simulation, down to hardware macrocell HDL description and implementation in CMOS technology. SensASIP features are described through two automotive sensor conditioning examples. Special focus is put on its increased flexibility and reduced design-effort vs. standard ASIC design approach and on its low complexity overhead vs. other state-of-art software-based solution
A Flexible Approach for Inductive Load Driver in Automotive Application
No full textThe current automotive IC sector counts hundreds of different systems, standard products or ASICs, for the inductive load drivers application. Many of them, such injector drivers, DC/brushless motor drivers, solenoid drivers, are designed to work in a specific operating mode, with fixed architecture and parameters. Since the need of different applications increases, a flexible approach to the design is mandatory. The state of the art offers only software-oriented systems to overcome these problems, which require embedded MCU. In this paper, an alternative system design for inductive load driver is proposed. It is based on an optimized and flexible architecture. With this flexible approach, it is possible to implement most of the topology scheme with regulation feedback and a programmable solution for shaping the current waveform into the loads
A low power Voice Activity Detector for portable applications
No full textVoice Activity Detectors (VADs) are used to enhance performances and to reduce the activation rate of speech recognition and key-word spotting applications. The last aspect is crucial for portable applications because it allows to save energy, increasing battery life. During last decades, VADs have been realized through hardware solutions to increase their speed in processing and to reduce their power consumption. However, the hardware implementation often represents a limit on the choice of the features to use, limiting the performances on recognition. This paper shows a low-power and low-area serial logistic regression classffier which uses the frame-energy, the maximum absolute signal finite difference and the maximum absolute squared signal finite difference over a frame as features. The system has been implemented on IGLOO nano Field Programmable Gate Array (FPGA), leading to power consumption of 0.559 mW and offering acceptable performances for its use as a preprocessor for speech recognition systems or a more sophisticated software VAD
Exploiting CCTV Camera System for Advanced Passenger Services On-board Trains
No full textThis work proposes to exploit the on-board closed-circuit television (CCTV) security system to enable advanced services not only for surveillance, but also for safety, automatic climate control, e-ticketing. The new system has minimal hardware and installation cost overheads, since it exploits the already installed CCTV cameras. In addition, for each wagon, an embedded acquisition and processing node (EAP) is used, composed by a video multiplexer, and by a digital signal processor that implements algorithms for advanced services such as: smoke detection, to give an early alarm in case of a fire, or people detection for people counting, or fatigue detection for the driver. The information is then transmitted from each EAP node to the train information system. The final terminals can be the tablets of the train staff, and/or visualization displays in each wagon in case of fire alarms for the passengers
Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation
Full text linkThis paper presents an improved VLSI (Very Large Scale of Integration) architecture for real-time and high-accuracy computation of trigonometric functions with fixed-point arithmetic, particularly arctangent using CORDIC (Coordinate Rotation Digital Computer) and fast magnitude estimation. The standard CORDIC implementation suffers of a loss of accuracy when the magnitude of the input vector becomes small. Using a fast magnitude estimator before running the standard algorithm, a pre-processing magnification is implemented, shifting the input coordinates by a proper factor. The entire architecture does not use a multiplier, it uses only shift and add primitives as the original CORDIC, and it does not change the data path precision of the CORDIC core. A bit-true case study is presented showing a reduction of the maximum phase error from 414 LSB (angle error of 0.6355 rad) to 4 LSB (angle error of 0.0061 rad), with small overheads of complexity and speed. Implementation of the new architecture in 0.18 μm CMOS technology allows for real-time and low-power processing of CORDIC and arctangent, which are key functions in many embedded DSP systems. The proposed macrocell has been verified by integration in a system-on-chip, called SENSASIP (Sensor Application Specific Instruction-set Processor), for position sensor signal processing in automotive measurement application
Design and quantization limits of root raised cosine digital filter
No full textThe Root Raised Cosine digital filter is a widely used pulse-shaping FIR filter in digital baseband communication systems. The design parameters of the filter implementation are strongly bound to the overall performance of the communication system. In this paper, we focus on a design analysis of the filter taking into account the filter band attenuation, the oversampling symbol interpolation, the roll-off factor, the span truncation and the fixed-point quantization of the coefficients to draw an outline strategy of the filter implementation and to show the design performance bounds as function of design parameters. To verify the design limits of the filter a MATLAB numerical investigation is presented, showing the main results. Finally, results of the synthesis on a xc7a15t Xilinx Artix-7 FPGA of a polyphase implementation of the filter were presented
Performance of digital adder architectures in 180nm CMOS standard-cell technology
No full textIn this paper, we present and compare the design and the performances of ten different implementations for a 16-bit adder in a 180nm CMOS standard-cell technology. Ripple carry adder, increment adder, triangle adder, uniform and progressive carry select adder, uniform and progressive carry bypass adder, conditional adder, ripple carry look ahead adder and hierarchical carry look ahead adder are taken into account. Every architecture is explained, highlighting the pros and cons. Finally, the results of area complexity, worst path timing and average power consumption for each implementation are shown
A design platform for flexible programmable DSP for automotive sensor conditioning
No full textIn automotive field the signal processing algorithms implemented on chips is getting more and more complex. This is leading to a growing area of digital blocks of sensor systems and to greater digital design effort. The work presented in this paper has been started in order to have a flexible software-oriented DSP in portfolio, quickly customizable for the current product and with the minimum area overhead. The design platform has three levels: the instruction set emulator model for a fast algorithm implementation and the instruction set definition, the bit-true and cycle-true model of the processor for a fine verification of the application firmware, and the RTL design of a three-stage pipeline μ-processor. The instruction set and the hardware resources of the μ-processor are easily customizable. A case study, a design aided by the platform, is presented. Synthesis results are discussed, being the area constraint one of the most significant
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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