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Analysis and design of high performance building blocks for phased array system in BiCMOS technology
Full text linkPhased array systems are spreading a lot in these years due to their higher performances respect to a single antenna. These systems have been progressively more and more employedin many fields such as satellite communications, high data rate links (emerging 5G technology), military and automotive radars. Initially they where only used for military applicationsdue to their higher costs and complexity. Thanks to the technology development and the researchers efforts, these days it is possible to integrate on the same chip an entire phased array system, leading to a drastic cost reduction. The explosive growth of the applications that use the phased array approach is the motivation behind this thesis, which deals with the analysis and design of high performance building blocks for phased array systems. The first part of this work gives a brief introduction on the phased array systems illustrating the working principle, the main tasks and issues of the design related to the need for high resolution and directivity of the antennas array. The second part of the thesis is dedicated to the analysis and design of building blocks for phased array systems. More in detail, the design of VGA (variable gain amplifier) and VCO (voltage controlled oscillator) will be described. VGAs are very important in the whole system because they are responsible for the array directivity and precision in the beam forming. The impact of the VGA performance impact on the phased array functionality is hence treated and analyzed. The phase behavior when the gain setting is changed is analyzed and discussed in depth. The aim of the design is to keep the phase of the signal constant for all the gain range variation in the frequency band of the amplifier. Several phase error compensation techniques have been studied and implemented. Some X -Band SiGe VGA have been realized and measured. The performance in terms of phase error as the gain is varied out-performs the state-of-the-art. In addition to X -Band applications, some work on the upcoming 5G Communication Network has been done. A Wide Band (15 − 40 GHz) Variable Gain Amplifier has been prototyped in SiGe BiCMOS technology and a 28 GHz VGA has been implemented in a 40 nm CMOS Technology. The VCO is the other fundamental building block that we take into consideration in this thesis. In this case, we focus our attention on the phase noise, a crucial parameter that is directly related to the performance of the phased array system. An in-depth analysis on the minimization of the phase noise has been done and some K-band (i.e. 18-27 GHz) VCOs have been realized in a SiGe bipolar technology. The VCOs feature a phase noise as low as -137 dBc/Hz at 10 MHz offset from the carrier. This result out-performs the state of the art if compared to other Silicon K-band Silicon-based VCOs. Only VCOs implemented using compound semiconductor technologies show better performance in terms of phase noise. However the technology cost is in this case, dramatically higher.
The work shows the feasibility of realizing high performance building blocks for phase array systems in Silicon technology. The possibility to integrate an entire phased array system on the same chip leads to a drastic cost reduction, overcoming the barrier that has stopped the development of this approach for several applications for many years. This a is crucial point for the development of next generation high data rate communication links and high precision automotive and military radars
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
No full textA 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS
No full textAn UWB impulse radio transmitter for ultra-low energy neural recording applications is proposed. The transmitter is designed for robust and efficient operation in the 7.25-8.5GHz band, supporting communication ranges in excess to 4m. Powered by a low-voltage 0.5V supply, prototypes in a 130 nm CMOS technology are able to transmit 2.76 pJ/b PPM-modulated pulses to the antenna at a 20Mb/s data rate with an outstanding 11.7% overall energy efficiency
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
No full textClass-C operation is leveraged to implement a K-band CMOS voltage-controlled oscillator (VCO) where the upconversion of 1/f current noise from the cross-coupled transistors in the oscillator core is robustly contained at a very low level. Implemented in a bulk 28-nm CMOS technology, the 12%-tuning-range VCO shows a phase noise as low as -112 dBc/Hz at 1-MHz offset (-86 dBc/Hz at 100 kHz offset) from a 19.5 GHz carrier while consuming 20.7 mW, achieving a figure of merit (FoM) of -185 dBc/Hz. The design is complemented by a theoretical investigation of 1/f noise upconversion caused by short-channel effects in the cross-coupled transistors, obtaining the first instance of a closed-form phase noise expression in the 1/f3 region
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation
No full textA 12 GHz VGA is presented that shows a gain control from -9 dB to 13 dB in a linear-in-dB fashion. As the gain is changed, the phase shift over the entire 10 to 14.4GHz bandwidth varies as little as <= 2 degrees due to a compensation circuitry that reduces the input-output phase shift sensitivity to gain variations. The VGA prototypes, implemented in a SiGe bipolar technology, show a noise figure of 5.1 dB, an IIP3 of -3dBm, and a power consumption of 83mW
A SiGe Bipolar VCO for Backhaul E-band Communication Systems
No full textA K-band SiGe bipolar VCO operating from 18.9 to 22.1GHz is presented. The oscillator features a phase noise as low as -136.5 dBc/Hz at 10MHz offset from the 22.1GHz carrierwhile drawing 10mA from the 3.3V supply. The VCO shows a state-of-the-art FOM of -188 dBc/Hz and an excellent FOMT of -192 dBc/Hz. The oscillator is tailored to the communication systems operating in the higher portion of the E-band. It is intended to be followed by a frequency multiplier by four, reported elsewhere
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators
No full textThis brief aims at finding the most appropriate frequency of operation of an integrated harmonic oscillator in order to maximize its spectral purity. To achieve this, a simple, yet accurate, scalable model is developed for the LC tank, that tracks the dependence of the parasitics on the inductance value. Using an ultra-scaled CMOS digital technology as a case study, the frequencies around 5 GHz are singled out as the sweet spot to minimize the phase noise
A 15.5–39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers
No full textA BiCMOS VGA for the emerging 5G mobile communication systems operates from 15.5 to 39GHz with a maximum 17 dB gain, features 43 dB gain variation, and, due to the use of compensation circuits, it shows a reduced phase shift variation, namely 3◦ up to 30GHz for a gain variation of 23 dB. The VGA NF is 3.6-9 dB, its IIP3 is -1 dBm, while the power consumption is 104mW
SiGe BiCMOS VCO with 27% tuning range for 5G communications
No full textA SiGe BiCMOS VCO with a transformer-coupled varactor operating from 12 to 15.9GHz is presented. The oscillator core features a phase noise as low as -117 dBc/Hz at 1MHz offset from the 14.2GHz carrier while drawing 8mA from the 3.3V supply. The VCO shows a state-of-the-art FoMT of -190 dBc/Hz. The trade-off for the technology selection is described in the introduction. The oscillator is tailored to the communication systems for the upcoming 5G applications. New radios that will operate from 6GHz to as high as 100 GHz may be needed
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations
No full textThe relentless development of next-generation communication and radar systems sets increasingly stringent requirements on the spectral purity of local oscillators. Decreasing phase noise is crucial to support efficient modulation formats with large symbol constellations, as well as to enable innovative radar applications, e.g., anti-collision, gesture recognition, and medical imaging. To minimize phase noise, bipolar transistors offer some advantages over ultra-scaled CMOS: higher supply voltage (thus larger oscillation amplitudes), lower 1/f noise, higher-Q passives (due to higher resistivity substrate and, possibly, thicker metals), and higher f T , f max for a given technology node, which results in a cost advantage for a variety of medium-volume applications (e.g., infrastructure transceivers). For a given supply voltage, a tank showing a smaller resistance at resonance yields lower phase noise. As a result, the minimum phase noise achievable by a single voltage-controlled oscillator (VCO) is ultimately bounded by the smaller realizable inductor displaying the highest Q. To achieve significantly lower phase noise levels, bilaterally coupling N oscillators [1-3] is a viable option. However, to fully preserve the 10log(N) phase-noise advantage, while avoiding undesired multi-tone concurrent oscillations, the coupling network must be carefully designed. This work presents a quad-core bipolar VCO achieving phase noise as low as -124dBc/Hz at 1MHz offset from the 15GHz carrier, -189dBc/Hz figure-of-merit (FOM), and 16% tuning range. Insights are given into the design of the resistive network employed to couple the four oscillators, a key element in achieving the reported performance
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