1,720,960 research outputs found
Device-Circuit Level Simulation Study of Three Inputs Complex Logic Gate Designed Using Nano-MOSFETs
No full textSimulation study on silicon-based nano-MOSFETs logic circuits is needed to add more knowledge on the nanoscale circuit performance. Therefore, in this paper, simulation study is carried out on three inputs complex logic gate transistor circuits with four different logic families, namely (i) nano-CMOS complex gate, (ii) nano-MOSFET loaded n-type nano-MOSFET complex gate, (iii) resistive loaded 733.8 ? nano-MOSFET complex gate, and (iv) pseudo n-type nano-MOSFET complex gate. NanoMOS is used to perform device simulation whereas WinSpice is used to perform circuit simulation. The difficulty faced during downscaling of nano-MOSFET is the realisation of low power high speed nano-MOSFET logic circuits design. Simulation output timing waveforms are used to analyse the timing characteristics of these complex logic circuits with Boolean expression. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET complex gate shows that theoretical modelling calculation of propagation delay and simulated propagation delay is 80% matched. With 10 nm nano-MOSFET complex logic circuits design, dynamic power reduction of 498 times and propagation delay improvement of 20 times are achieved when compared with a typical 120 nm MOSFET logic circuit
Simulation study on the electrical performance of equilibrium thin-body double-gate nano-MOSFET
No full textThis paper presents a numerical simulation study for electrical characteristics of doublegate (DG) nano-MOSFET at equilibrium thin-body condition. The electrical characteristics which are studied include subband energy (including unprimed and primed subbands), 2D electron density at 77K and 300K ambient temperatures, transmission coefficient, average electron velocity and ballistic current. The ranges of silicon body thickness TSi are 1.0 nm, 1.5 nm and 2.0 nm. The electron transport models used in simulation tool covered quantum model and classical model. Simulation output data are also compared with theoretical discussion
NANO-MOSFETs Implementation of different logic families of two inputs NAND gate transistor level circuits: a simulation study
No full textIn this paper, simulation study has been carried out on two inputs logic NAND transistor circuits with four different logic families, namely (i) nano-CMOS NAND gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NAND gate, (iii) resistive loaded nano-MOSFET NAND gate, and (iv) pseudo nano-MOSFET NAND gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on type of logic families. The problem with downscaling of nano-MOSFET is the implementation of low power high speed nano-MOSFET transistor circuit. Simulated timing diagrams for input and output waveforms showed correct logical NAND gate operations for all four logic families. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET NAND gate shows that theoretical modeling calculation of rise time (tr), fall time (tf) and maximum operating frequency (fmax) are reasonably matched simulated output result of WinSpice. All the logic family circuits studied shown reduction in dynamic power when MOSFET is downscaled to nanometer regime
Device and Transistor Level Circuit Performance Analysis of Nanoscale Mosfet
Get PDFWhen nano-MOSFET structural dimension is downscaled to nanometer regime, quantum effects become obvious. This small channel length nano-MOSFET reduces electron transit time from source to drain. Owing to small dimension, its smaller capacitance would result lower power dissipation.
When applying this nano-MOSFETs in designing resistive loaded logic gates, lower power dissipation high speed logic gates are produced. The first objective of this thesis is to prove the optimized parameters of n-channel nano-MOSFET formulated by Purdue University using nanoMOS software also developed by Purdue University. The nano-MOSFET parameters involved include channel length, temperature, gate contact work function, gate
underlap, intrinsic channel and gate length. They are optimized by characterizing the electrical quantities such as subband energy levels, electron density profile, transmission coefficient, leakage current and threshold voltage aiming to produce low potential barrier height, unity transmission coefficient, low leakage current and small threshold voltage. The second objective is to
characterize the dc and ac parameters for the logic gates designed with this optimized parameters n-channel nano-MOSFET by simulation using WinSpice and HSPICE simulators. The logic gates timing characteristics such as risetime, fall time and propagation delay are evaluated by using simulators. The power dissipation reduction is observed from simulation results.
This research project has successfully achieved the objectives. The final optimized parameters of the nano-MOSFET are channel thickness of 1.5 nm, temperature of 300 K, gate contact work function of 4.188 eV, no gate
underlap, gate length of 10 nm and intrinsic channel. The criteria used to justify the above device optimization are low threshold voltage of 0.20 V, ballistic efficiency of 0.96 and low leakage current of 5.312x10-2 μA/μm. The
ac parameters mainly rise time, fall time and propagation delay of the logic circuits have been analyzed and the dc parameters analysed are VOH, VOL, VIH, VIL, VM, VLS, VTW,VNMH, VNML, VNSH, VNSL, VNIH and VNIL. The value of
lower power dissipation and shorter propagation delay of logic gates achieved are in the range of microwatts (μW) and femtosecond (fs), respectively. In future work, the similar study on the characteristics p-channel nano-
MOSFET can be done so that it can combine with n-channel nano-MOSFET to design and characterize the nano-complimentary MOSFET (nano-CMOS) logic gates
A comparative study of quantum gates and classical logic gates implemented using Solid-State Double-Gate Nano-MOSFETs
No full textLink to publisher's homepage at http://ijneam.unimap.edu.my/The purpose of this paper is to compare the operations of silicon-based solid-state
quantum computer with classical logic gate made of double-gate (DG) nano-MOSFETs.
Quantum gates, such as quantum NOT gate, controlled-NOT (CNOT) and quantum register
are studied. On the other hand, classical computer gates, such as NOT gate, NOR gate,
NAND gate, XOR gate and XNOR gate are described. Silicon-based solid-state quantum
computer operates well at extremely low cryogenic temperature (77K) as shown by
oscillation of electron density profiles of the silicon-based nanodevices. Unitary matrix
which specifies a valid quantum gate is proven in this study. The intrinsic delay of the
classical NOT gate is calculated from simulation output data and the current-voltage (I-V)
characteristic of the DG nano-MOSFET, which is used to construct the NOT gate, is plotted
and studied. The motivation of this study is to investigate ways to implement quantum
computer with silicon-based DG nano-MOSFET implanted with phosphorus donor atoms
Simulation Study of n-type Double-Gate Nano-MOSFET with Arbitrary Wafer Orientations and Any Channel Materials
Get PDFIn this paper, the technique for quantum mechanically simulating a double-gate (DG) nano-MOSFET with arbitrarily oriented wafer directions and various channel materials is presented. The problem with arbitrarily oriented wafer directions and any channel materials is that the misalignment of principal axes of conduction bands ellipsoids and devices axes causes the matrix and so effective mass equation (EME) become cumbersome to solve. This drawback is overcome by transforming the main axes of the conduction band ellipsoids of the nano-MOSFET to align properly with the device axes, that are transport, confinement and width directions. This transformation technique is discussed theoretically, generally and then simulated specifically for a 10 nm n-type DG nano-MOSFET designed using Silicon (Si) wafer orientation of (100) direction. Two current-voltage (I-V) equations are derived and the calculated on-state current value, are compared with theoretically simulated data 2.500x103 µA/µm. The first and second current model produce of 2.182x103 µA/µm and 2.548x103 µA/µm, respectively. The second model is more accurate since it treats the electron flow as ballistic. This transformation technique enables device engineers to use any device simulator with EME model to study the carriers transport properties of MOSFET with any channel materials (Si, Ge and GaAs) and arbitrary wafer orientations ((100), (110) and (111)). This paper focuses specifically on Si with (100) wafer
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
- …
