1,720,973 research outputs found
A Model to Understand Current Consumption, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers
No full textIn this work, the effect of digital CMOS technology
down scaling on the performances of MOS Current Mode Logic
frequency dividers is addressed. A fast and effective methodology
to design the dividers is presented. The insight given by the
methodology is then exploited to study the down scaling of
MCML dividers by considering two CMOS technologies representative
of the 130nm and 90nm technology nodes. The model
provides quantitatively accurate predictions of the advantages
of scaling on current consumption and maximum frequency of
operation
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications
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Modeling, Design and Characterization of a new low Jitter Analog Dual Tuning LC-VCO PLL Architecture
No full textThis paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-mu m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm(2) and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators
No full textThis brief aims at finding the most appropriate frequency of operation of an integrated harmonic oscillator in order to maximize its spectral purity. To achieve this, a simple, yet accurate, scalable model is developed for the LC tank, that tracks the dependence of the parasitics on the inductance value. Using an ultra-scaled CMOS digital technology as a case study, the frequencies around 5 GHz are singled out as the sweet spot to minimize the phase noise
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars
No full textThe need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique
No full textThis paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
No full textThis work describes the design of a transmitter for a
10 Gbps serial interface to be used in automotive Electronic Control
Units. The data rate is chosen in order to assess the design
challenges in automotive environment at this frequency. The focus
will be mainly on challenges related to transistor level design
using a standard 28 nm technology, nevertheless a system level
overview will be also given. The proposed transmitter features
feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors,
plus the main tap), whose strength is programmable with
16 discretization steps, optimizing the transmitter adaptability
with reduced area. The proposed architecture is also able to
tune its output impedance independently from the choice of the
weights of the equalization tap. It features a 300 mV peak-topeak
eye diagram with 16 equalization levels and achieves a
remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit
for the predriver+driver)
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces
No full textA 19.5 GHz 28 nm CMOS class-C VCO with reduced 1/f noise upconversion
No full textClass-C operation is leveraged to implement a K-band CMOS VCO where the upconversion of the 1/f noise from the core transistors is robustly contained at a minimal level. Implemented in a bulk 28 nm CMOS technology,the VCO shows a phase noise as low as -108.5 dBc/Hz at 1 MHz offset (-83 dBc/Hz at 100 kHz offset) from the 19.5 GHz carrier,while consuming 14.4 mW and featuring a 12% tuning range
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