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A CMOS readout circuit for microstrip detectors
No full textIn this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation
The analog channel for the readout of the outer layers of the SuperB SVT
No full textIn this work, we present the design and the results of the analog channel of the readout circuit for the outer layers of SuperB Silicon Vertex Tracker (SVT). In these layers, the strip detectors have a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. To fulfill the noise level and efficiency requirements, a compromise on the best peaking time has been investigated. The ASIC is composed by a classical processing scheme, composed by a preamplifier, shaping amplifier and TOT for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit foresees the possibility to select the peaking time of the shaper (250, 375, 500 and 750 ns). In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The first prototype has been fabricated in the 130nm IBM technology which is considered intrinsically radiation hard. The first results of the experimental characterization of a produced prototype are here presented
Analog front-end electronics for the outer layers of the SuperB SVT: Design and expected performances
No full textThe Silicon Vertex Tracker (SVT) of the new SuperB collider will be composed of 6 different detector layers [1]. The innermost layer (LO) will be composed by striplets or pixels [2]; the other 5 detector layers will be double-sided long-strip detectors. The strip geometries and the foreseen hit-rates will change according to the different layers. As a consequence, different optimization of the analog readout electronics is needed in order to provide high detection-efficiency and low noise level in the different layers. Two readout ASICs are currently developed, one for layers 0-3, another for layers 4 and 5; they differ mainly in the analog front-end.
In this work, we present the design and the expected performances of the analog front-end for layers 4 and 5. For these layers, the strip detectors show a very high stray capacitance and high series resistance. In this condition, the noise optimization is our primary concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been found. We will present the design of preamplifier and shaper and the results of simulation of noise performance and efficiency (with the expected background rates). In addition, the design of the time-over-threshold and its use to correct the time-walk of the event trigger is discussed as well as the achievable timing accuracy of the circuit
A front-end stage with signal compression capability for XFEL detectors
No full textIn this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range
A CMOS self-triggered gated integrator circuit for SiPM readout in SPECT applications
No full textEnergy resolution plays a major role in multitracer SPECT detectors, as spectral lines emitted by different radionuclides have to be distinguished. In the electronic circuit for the readout of SiPMs used in a SPECT system, the processing filter choice is therefore essential to provide the best achievable energy resolution. Gated integrator filter was identified as an excellent candidate for this kind of application, mainly thanks to its capability to reduce ballistic deficit in the signal processing, allowing for a quasi-complete light collection with a filtering time considerably shorter with respect to the ones needed by time-invariant circuits. A single-channel prototype circuit in CMOS 0.35 μm technology was developed to validate preliminary studies. The circuit features a current buffer input stage with the possibility to tune the input voltage in a 1 V range with 6 bit resolution and a filtering section to integrate the signal rejecting the baseline component originated by the dark count current of the SiPM. A discriminator block recognises the arrival of the signal and initiates the integration phase; a control section generates the gating interval, selectable in a range between 80 ns and 15 μs to cope with various scintillator types, and manages the different timing phases of the circuit. A comparison between the energy resolution achievable using both a time invariant RC filter and a gated integrator one is done, showing, for the latter, a better expected energy resolution performance at the 140 keV 99mTc peak. Preliminary experimental results of the prototype when coupled to a SiPM are reported
A Simple Technique for Signal Compression in High Dynamic Range, High Speed X-ray Pixel Detectors
Get PDFNew X-ray pixel detectors are required to cope with the demanding requirements from XFEL sources, in terms of high speed and high dynamic range. Such detectors have to provide low electronics noise to allow single photon detection at low signal intensities. At high photons intensity, a signal compression technique may be introduced to allow the detection system to cope with the required dynamic range. In this work, we propose a very simple front-end (FE) solution based on an input PMOS transistor placed on the CMOS readout chip connected to the pixel detector. The FE is optimized for low-noise readout of X-ray photons at low intensities. A gain compression when the signal intensity increases is obtained by operating the PMOSFET in the triode regime thanks to a resistor placed between the transistor and the current-readout filter. The larger is the transistor signal, the larger is the voltage drop on the resistor which pushes the transistor to operate more in triode regime at lower gain, producing a compression in the overall FE response. The FE working principle and the first experimental results obtained with a first prototype realized in the 130 nm IBM technology are presented
Progetto di un circuito integrato di front end per rivelatore a microstrip di particelle
No full textLAUREA SPECIALISTIC
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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