1,721,000 research outputs found
The Combined Perceptron Branch Predictor
No full textPrevious works have shown that neural branch prediction techniques achieve far lower misprediction rate than traditional approaches. We propose a neural predictor based on two perceptron networks: the Combined Perceptron Branch Predictor. The predictor consists of two concurrent perceptron-like neural networks, one using as inputs branch history information, the other one using program counter bits. We carried out experiments proving that this approach provides lower misprediction rate than state-of-the-art conventional and neural predictors. In particular, when compared with an advanced path-based perceptron predictor, it features 12% improvement of the prediction accuracy
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
No full textThis paper proposes a system-level cycle-based framework to model and design heterogeneous multiprocessor systems-on-chip (MPSoC), called GRAPES. The approach features flexibility and modularity maintaining high simulation speed despite modeling at cycle level. Intellectual property (IP) system modules can be described as C++or System C entities and they are wrapped into C++ objects, called plug-ins. Plug-ins, that are modeled by the transaction level modeling (TLM) style, are managed by the GRAPES kernel, which is the core of the simulation framework. GRAPES structural approach permits to easily model run-time reconfiguration and power modeling. Furthermore, GRAPES has been used to model and to simulate a case study: a scalable and heterogeneous MPSoC based on network-on-chip (NoC) interconnect
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAs
No full textThis paper presents the design of a JPEG encoder which exploits this feature. We propose a mixed HW/SW architecture, where most compute-intensive components of the application are mapped to application-specific HW cores. These cores can be alternated on the FPGA, by means of internal dynamic reconfiguration. Our purpose is to describe a real-world application of reconfigurable computing, illustrating how this approach allows to save area with negligible performance overhead
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures
No full textThe need for fast but secure cryptographic systems is growing bigger. Therefore, dedicated hardware for cryptography is becoming a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not safe. Attacks based on power consumption and electromagnetic Analysis, such as SPA, DPA and EMA have been successfully used to retrieve secret information stored in cryptographic devices. Besides performance in terms of area and throughput, designer of embedded cryptographic hardware must worry about the leakage of their implementations.
This paper deals with the leakage that occurs in the SW computation of AES on platforms equipepd with a cache memory through the miss events, which may allow to infer the secret key
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
Full text linkMultimedia applications, and in particular the encoding and decoding of standard image and video formats, are usually a typical target for Systemson- Chip (SoC). The bi-dimensional Discrete Cosine Transformation (2D-DCT) is a commonly used frequency transformation in graphic compression algorithms. Many hardware implementations, adopting disparate algorithms, have been proposed for Field Programmable Gate Arrays (FPGA). These designs focus either on performance or area, and often do not succeed in balancing the two aspects. In this paper, we present a design of a fast 2DDCT hardware accelerator for a FPGA-based SoC. This accelerator makes use of a single seven stages 1D-DCT pipeline able to alternate computation for the even and odd coefficients in every cycle. In addition, it uses special memories to perform the transpose operations. Our hardware takes 80 clock cycles at 107MHz to generate a complete 8x8 2D DCT, from the writing of the first input sample to the reading of the last result (including the overhead of the interface logic). We show that this architecture provides optimal performance/ area ratio with respect to several alternative designs
An Efficient Synchronization Technique for Multiprocessor Systems on-Chip
Full text linkThis paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future mobile systems. We suggest the architecture of the memory controller optimized to minimize synchronization overhead. The proposed solution is based on the idea of performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks), locally in the memory. We introduce a HW module, which augments the memory controller, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For an 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 25% energy saving with respect to synchronization based on the caching of the synchronization variables and directory-based coherency protocol. Furthermore, we prove the scalability of the proposed approach when the number of processors increases
A novel fuzzy expert system to assess the sustainability of the viticulture at the wine-estate scale
No full textThe wine industry is definitely committed in sustainability: the stakeholders’ interest for the topic is constantly growing and a wide number of sustainability programs have been launched in recent years. Most of these programs are focusing on the environmental aspects as environmental sustainability indicators, greenhouse gases emissions and the use of Life Cycle Assessment methodology. Among the environmental indicators the carbon and the water footprint are often used. These indicators, while being useful to assess the sustainability performance of the winegrowing farms, do not take into account important aspects related to the agronomic management of the vineyard. To fill this gap a new indicator called “Vigneto” (Vineyard in Italian language) has been developed. “Vigneto” is a multidimensional indicator to evaluate the sustainability of management options adopted at field scale. It considers the main agronomic aspects, which can have an impact on the environment. These include (i) pest management, (ii) soil management (erosion and compaction), (iii) fertility management (soil organic matter management and fertilizer application), (iv) biodiversity management. Those aspects have been related by fuzzy logics and implemented in web GIS software. The application of the model allows obtaining a general judgment of the agronomic sustainability of the vineyard management: the judgment varies from “A” (excellent) to “E” (completely unsustainable). The produced model was validated and tested by four Italian wine estate. The model output reports that the tested wineries have different management strategies: producers manage vineyards in different ways, depending on the different geographical position. The main differences are related to the soil management and to the presence of natural areas different from vineyard. The developed model can be defined as an environmental decision support system that can be used by wine companies’ technicians to define the vineyard practices sustainability performance and support them in the definition of more sustainable management practices
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA
Full text linkThis paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properlyallsynchronize the local copies with the shared memory image. This idea can be applied both to a scratchpad-based architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset
Lightweight DMA management mechanisms for multiprocessors on FPGA
No full textThis paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local mem-ory of each processor. The system integrates all standard DMA primitives via a fast Application Programming Inter-face (API) and relies on interrupts having also the possibil-ity to manage a command list. This interface allows to pro-gram the embedded multiprocessor architecture on FPGA with simple DMAs using the same DMA techniques adopted on high performance multiprocessors with complex DMA controllers. Several experiments demonstrate the perfor-mance of our solution, allowing 57 % improvement on the execution time of a selected set of benchmarks. We fur-thermore show how some DMA programming techniques (double and multi-buffering) can be effectively used within our platform, thus easing the design and development of the hardware and the software in a reconfigurable DMA-based environment.1
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs
Full text linkThis paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex
interconnect (Network-on-Chip), targeted at future poweref
cient systems. The proposed solution is based on the idea
of locally performing synchronization operations which require
the continuous polling of a shared variable, thus featuring
large contention (e.g. spin locks). We introduce a HW
module, the Synchronization-operation Buffer (SB), which
queues and manages the requests issued by the processors.
Experimental validation has been carried out by using
GRAPES, a cycle-accurate performance/power simulation
platform. For 8-processor target architecture, we show
that the proposed solution achieves up to 40% performance
improvement and 30% energy saving with respect to synchronization based on directory-based coherence protocol
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