1,720,981 research outputs found
Dynamic loading and task migration for streaming applications on a composable system-on-chip
No full textMPSoCs offer more and more processing capability to embedded systems. As a result, an increasing number of applications run on one system, sharing MPSoC resources. Some of these applications are streaming applications and may have real-time demands, e.g., guaranteed throughput, hence their temporal behavior has to be verified at design-time. Moreover, applications may start and stop at run-time, creating a set of use-cases. The interference at shared resources introduces fluctuations in the temporal behavior of applications that may invalidate the results of the design-time verification. The CompSoC platform eliminates this interference by virtualizing shared resources, enabling independent, per-application design and verification. However, currently CompSoC requires that the entire source code to be compiled and linked into one executable. This code may belong to different applications and the developers of these applications have to hence share their source code, which is not always possible due to IP protection issues. Furthermore, resources may be wasted because a core's memory must be sufficient for all applications that ever run there and not only for the most demanding use-case. In this thesis we augment CompSoC with dynamic loading and task migration mechanisms that allow separation of executables per application, enable memory reuse between use-cases, and, in general, increase flexibility, making possible, e.g., workload balancing. We implement this mechanism at application level, hence in a separate system application. This ensures that loading and migration do not interfere with running applications. More precisely, applications have independent temporal behavior from the moment they start until they are paused or stopped. Moreover, the dynamic loading and task migration processes execute in bounded time, thus are predictable, which makes them suitable for streaming applications. We implemented the dynamic loading and task migration on an FPGA prototype of CompSoC. Experiments indicate that that the temporal behavior of a running application is not influenced by dynamic loading and task migration of other applications. We investigate the performance of the dynamic loading process for a jpeg decoder and an image rotation application and we detail the performance overhead involved in task migration. Furthermore, our implementation does not affect the critical operating system execution and the memory footprint overhead is only 4KB.Embedded SystemsMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Task centric memory management for an on-chip multiprocessor
No full textElectrical Engineering, Mathematics and Computer Scienc
Porting GCC to a Clustered VLIW Processor
No full textA clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this thesis, we describe how we ported the GNU Compiler Collection (GCC), a popular free compiler, to a clustered version of the Embedded Vector Processor (EVP), a VLIW vector processor being developed at ST-Ericsson. The aim of this thesis project was to produce a prototype GCC back-end for the clustered EVP, and to benchmark it. In this report we describe our implementation in detail, presenting an approach that tackles the problem of clustering, commenting upon existing algorithms, choosing and improving upon one of them while designing a GCC RTL optimization pass for cluster assignment. We visually inspected our prototype for functional correctness, and benchmarked it against the original EVP design and the corresponding production compiler. Our measurements show a 27% speed-up in compute intensive components of the EVP's W-CDMA workload.Computer EngineeringElectrical EngineeringElectrical Engineering, Mathematics and Computer Scienc
Improved static data-flow model for TDM scheduler
No full textA streaming application like software defined radio (SDR) executed on a heterogeneous multi-processor system on chip (MPSoC) consists of various transceiver jobs that have to be scheduled on different processors concurrently. The hard real time performance requirements of these jobs can be guaranteed on the multi-processor system on chip (MPSoC) using a Time Division Multiplexing (TDM) scheduler for each processor. The TDM scheduler allocates a fixed amount of time slot for each job and removes the timing inter-dependence between the concurrently executing jobs. In order to guarantee that a job scheduled using a TDM scheduler would meet its deadlines, temporal analysis can be performed by modelling an application as a data-flow graph, called as an application graph. Scheduling framework maps nodes of the data-flow graph, called actors, on to the processors. It generates a schedule or an order in which actors of an application can execute on a processor. This order is called a static order. Data-flow model for a TDM scheduler is a timed data-flow graph which uses the TDM scheduler settings to predict worst case finish times of a job scheduled on a TDM scheduler. Using this mapping information and a data-flow model, an analysis graph is obtained from the application graph by replacing each application actor by a data-flow model and is analysed for its temporal behaviour. Various such data-flow models, e.g., the latency rate model, are proposed in the literature, but they over-estimate the worst case finish time of an application. This over-estimation causes over-allocation of resources on the processor. In this thesis, we propose a data-flow model based on multi-rate data flow (MRDF) graph, called as a multi-rate model, that is conservative and more accurate than the existing models. We provide a detailed analysis of the multi-rate model and prove that the model is conservative. We also show that the multi-rate model provides worst case finish times that are more accurate than existing models like the latency rate model. We implemented the multi-rate model, simulation of the TDM behaviour and techniques to reduce the utilizations of the processors on an existing data-flow analysis tool developed at ST Ericsson. We used our implementation to study the impact of improved accuracy in the estimation of the finish times of the application tasks due to the multi-rate model. The reductions in the processor utilization obtained using the multi-rate model were found to be better than the latency rate model and in some cases, better than the simulation technique. The experimental results show that the improved modelling accuracy helped us to achieve up to 40\% reduction in the utilization of a processor, over the latency rate model based method for a WLAN application. Thus, the multi-rate model is a more accurate model for the analysis of the TDM scheduler arbitration as compared to the state-of-the-art.Embedded SystemsMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Tile-Based rasterization on an embedded Tile-based MPSoC
No full textGraphics on a computer are often handled by a graphics pipeline. Rasterization is an important stage in this pipeline. It converts the basic elements of computer graphics, triangles, into the basic elements of a screen, pixels. This stage is very computation intensive and has a large memory footprint. The last decade a lot of research has been dedicated to tile-based rasterization. This technique divides an image into smaller images called tiles. These can be stored on a smaller memory, hence reducing the memory footprint of the rasterization process. Several software and hardware implementations of tile-based rasterization exist. They use a single general purpose processor, or make use of multiple specialized cores, such as Graphical Processing Units (GPUs). Although GPUs prove to be very fast in graphical applications, their effectiveness in running other applications is limited. This is a potential drawback in embedded systems where the available resources are very limited. In Embedded Systems typically Multiple Processors are used in a System on Chip, an MPSoC. This work will make a parallelization study to investigate the performance of rasterization on a MPSoC. To perform this study we modify a tile-based rasterizer to make efficient use of multiple embedded processors. This modified rasterizer is used to evaluate the impact of various configurations on the execution time of the rasterizer. For example the size of an image tile, the size of the communication buffer and the number of processors will be varied in our experiments. Increasing the size of an image tile proves to decrease the execution time only to a certain point, after which the execution time will start to increase. Furthermore, using a larger communication buffer increases the load balancing and decreases the execution time. It is concluded that with the right load balancing adding processors to the system will decrease the time needed to rasterize an image.Computer EngineeringComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Task Scheduling Methods for Composable and Predictable MPSoC
No full textMultiprocessor Systems on a Chip (MPSoCs) are suitable platforms for executing complex embedded applications. To reduce the cost of the hardware platform, applications share resources, which may result in inter-application timing interference due to resource request conflicts. Bounding or prohibiting this interference is crucial, as the timing of real-time applications has to be predicted in each possible case. Resources that allow sharing without application interference are denoted as composable. Composability is a desired platform property, as it enables the design and analysis of applications in isolation, and their integration with linear effort. Previous work demonstrates composability for different resources, i.e., processor, interconnect, memory. Processor composability is achieved by utilizing an Operating System (OS) that schedules fixed duration task slots, using a two-level, hierarchical approach. First, the OS determines which application owns the next slot following a strict, preemptive Time Division Multiplexing (TDM) policy, and then it picks and schedules a task of that application. As scheduling decisions are taken exclusively at slots borders, when a task finishes before its slot depletes, the time left is wasted. This may result in low processor utilization for streaming applications for which the execution of a task may start after its predecessor tasks have finished. In this work we propose a new task scheduling strategy, namely application-space task scheduling that eliminates wasted slot time. We make use of the fixed duration slots and the application TDM, to preserve composability, but the application invokes the task scheduler immediately after each task finish, inside its slot. As the application-space task scheduling strategy alone may not support all types of task scheduling, e.g., preemptive, we propose to combine OS-space and application-space scheduling on the same processor. To experimentally investigate the composability and performance of our scheme we survey existing benchmarks for the embedded domain, and build a workload consisting of two streaming applications and a synthetic application. We executed these applications on an MPSoC with two processor tiles, a monitor tile, all connected by a Æthereal NoC. Our experiments indicate that mixing application-space and OS-space task schedulers is composable. Furthermore, the application-space task scheduling achieves 17% to 40% better performance than the OS-space task scheduling for the streaming applications exercised.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
- …
