10 research outputs found
Smart behavioral netlist simulation for SEU protection verification
No full textSchulz S, Beltrame G, Merodio-Codinachs D. Smart behavioral netlist simulation for SEU protection verification. Esa Sp. 2008:406-411.This paper presents a novel approach to verify the correct implementation of Triple Modular Redundancy (TMR) for the memory elements of a given netlist using formal analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour even for large designs. This is achieved by applying a divide et impera approach, splitting the circuit into smaller submodules without loss of generality, instead of applying formal verification to the whole netlist at once. The methodology has been applied to a production netlist of the LEON2-FT processor that reported errors during radiation testing, successfully showing its TMR implementation issues
SETA: A CAD tool for Single Event Transient Analysis and Mitigation on Flash-based FPGAs
Get PDFFlash-based Field Programmable Gate Array (FPGA) devices are nowadays golden cores of many applications especially in space and avionic fields where reliability is becoming an important concern. In particular, for Flash-based FPGAs when adopted in those applications, the main concern is radiation-induced voltage glitched know as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool has been developed in order to evaluate the sensitivity of the implemented circuit regarding SET and to mitigate their effects. The proposed tool has been applied to an industrial design adopted by the EUCLID space mission including more than ten different modules. The experimental results demonstrated the feasibility and efficiency of proposed tool
Accurate Mitigation of Single Event Effects on Flash-based FPGAs: A new Design Flow
No full textWe propose a new design flow for implementing circuits hardened against SET effects af- fecting Flash-based FPGAs. Experimental results on RISC microprocessors show an in- crease of robustenss of more than 70% wrt traditional mitigation approache
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA platforms
No full textRobustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA
No full text
Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA
No full textAnalysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
No full textSRAM-based FPGAs are increasingly relevant in a growing number of safety-critical application fields, ranging from automotive to aerospace. These application fields are characterized by a harsh radiation environment that can cause the occurrence of Single Event Upsets (SEUs) in digital devices. These faults have particularly adverse effects on SRAM-based FPGA systems because not only can they temporarily affect
the behaviour of the system by changing the contents of flip-flops or memories, but they can also permanently change the functionality implemented by the system itself, by changing the content of the configuration memory. Designing safety-critical applications requires accurate methodologies to evaluate the system’s sensitivity to SEUs as early as possible during the design process. Moreover it is necessary to detect the occurrence of SEUs during the system life-time. To this purpose test patterns should be generated during the design process, and then applied to the inputs of the system during its operation. In this thesis we propose a set of software tools that could be used by designers of SRAM-based FPGA safety-critical applications to assess the sensitivity to SEUs of the system and to generate test patterns for in-service testing. The main feature of these tools is that they implement a model of SEUs affecting the configuration bits controlling the logic and routing resources of an FPGA device that has been demonstrated to be much more accurate than the classical stuck-at and open/short models, that are
commonly used in the analysis of faults in digital devices. By keeping this accurate
fault model into account, the proposed tools are more accurate than similar academic and commercial tools today available for the analysis of faults in digital circuits, that do not take into account the features of the FPGA technology..
In particular three tools have been designed and developed: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, a simulator of SEUs affecting the configuration memory of an SRAM-based FPGA system
for the early assessment of the sensitivity to SEUs; (ii) UA2TPG: Untestability Analyzer
and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, a static analysis tool for the identification of the untestable SEUs and for the automatic generation of test patterns for in-service testing of the 100% of the testable SEUs; and (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, a Genetic Algorithm-based Environment for the generation of an optimized set of test patterns for in-service testing of SEUs. The proposed tools have been applied to some circuits from the ITC’99 benchmark. The results obtained from these experiments have been compared with results
obtained by similar experiments in which we considered the stuck-at fault model, instead
of the more accurate model for SEUs. From the comparison of these experiments we have been able to verify that the proposed software tools are actually more accurate than similar tools today available. In particular the comparison between results obtained using ASSESS with those obtained by fault injection has shown that the proposed fault simulator has an average error of 0:1% and a maximum error of 0:5%, while using a stuck-at fault simulator the average error with respect of the fault injection experiment has been 15:1% with a maximum error of 56:2%. Similarly the comparison between the results obtained using UA2TPG for the accurate SEU model, with the results obtained for stuck-at faults has shown an average difference of untestability of 7:9% with a maximum of 37:4%. Finally the comparison between
fault coverages obtained by test patterns generated for the accurate model of SEUs and the fault coverages obtained by test pattern designed for stuck-at faults, shows that the former detect the 100% of the testable faults, while the latter reach an average fault coverage of 78:9%, with a minimum of 54% and a maximum of 93:16%
