46 research outputs found
Hyphoporus solieri
No full text<i>Hyphoporus solieri</i> (AUBÉ 1838) <p> <i>Hydroporus solieri</i> AUBÉ 1838: 554 (original description); SHARP 1882: 391.</p> <p> <i>Hyphoporus solieri</i> (AUBÉ 1838): RÉGIMBART 1895: 37; ZIMMERMANN 1920: 73; 1930: 115; GUIGNOT 1959a: 337; ALFIERI 1976: 33; AL- HOUTY & ANGUS 1999: 184; ZALAT et al. 2000: 28; NILSSON 2012 (distribution).</p> <p> This species has been described by AUBÉ (1838: 554) from " Égypte " (African part and Sinai). So far it was, additionally, known from Kuwait and Saudi Arabia (NILSSON 2012). SHARP (1882: 391) gave also the areas " Persia " and "northern India " which later on, however, have not been accepted by any author and are most probably due to a misidentification of another species. We can report the following record from close to the Iraqi border: 4, 4, " 12.9.2010 Iran, Khuzestan, 8 km SE Abadan, altitude 8 m, Darvishzadeh leg., ca. 30.29N 48.36E, pond" (CHF) (Fig. 23; square 1). This is the f i r s t r e c o r d of <i>H. solieri</i> from Iran. To our knowledge a photo of the habitus of this species has never been provided before (Fig. 14).</p> <p> <b>Notes</b>: We could not recognise extern morphological differences to specimens from Egypt; the male genitalia also equal those of Egyptian specimens. It seems to be likely that the species occur also in the southern parts of Iraq.</p>Published as part of <i>Ewalka, Pešić, V. & Darvishzadeh, I., 2012, Faunistic notes on some Hydradephaga from the Khuzestan, Hormozgan and Sistan & Baluchestan provinces in Iran, with descriptive notes on the female of Glareadessus franzi WEWALKA & BISTRÖM 1998 (Coleoptera, Dytiscidae, Noteridae), pp. 1057-1070 in Linzer biologische Beiträge 44 (2)</i> on page 1061, DOI: <a href="http://zenodo.org/record/5328829">10.5281/zenodo.5328829</a>
REPORT 2018 | Progetto Article processing charges (APCs) Monitor @UNIMORE 2018 [APCs Monitor Project @UNIMORE 2018]
No full text[partially AI generated] The "APC Monitor @UNIMORE" project aims to track APC spending at the university level over time. The primary objectives include identifying, quantifying, and monitoring UNIMORE's expenses for open access, encouraging specific publishing behaviors among UNIMORE researchers, and participating in the European project Open APC. This report presents the preliminary findings of the analysis of the state of the art regarding the registration of APC-related expenses in U-GOV. It includes a detailed examination of the methods used to record APCs, an analysis of the information and keywords in the "Description" field of financial documents related to APC expenses, and a discussion of activities carried out, such as a preliminary survey with department secretaries and an analysis of detailed descriptions of financial documents. The analysis concludes with proposed actions, including the creation of a new accounting code for scientific contributions, the discontinuation of the current code for "Estratti e reprints articoli scientifici", training for staff on the use of new codes, and guidelines for entering author names and article/volume titles in the description field of financial documents. In summary, the report emphasizes the need for a systematic approach to monitoring APCs, the importance of accurate data collection, and proposes specific actions to enhance the efficiency of APC monitoring at the university level
Integrated Schedulability Analysis
No full textDeliverable 5.3 of the project HERCULES "High-Performance Real-Time Architectures for Low-Power Embedded Systems", funded by the European Union’s Horizon 2020 research and innovation programme under grant agreement: 688860.
The purpose of this deliverable is to provide a description and analysis of the software techniques that allows predictable and efficient application hosting and scheduling on both CPU and GPU
Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs
No full textHigh-performance embedded platforms are increasingly adopting heterogeneous systems-on-chip (HeSoC) that couple multi-core CPUs with accelerators such as GPU, FPGA, or AI engines. Adopting HeSoCs in the context of real-time workloads is not immediately possible, though, as contention on shared resources like the memory hierarchy—and in particular the main memory (DRAM)—causes unpredictable latency increase. To tackle this problem, both the research community and certification authorities mandate (i) that accesses from parallel threads to the shared system resources (typically, main memory) happen in a mutually exclusive manner by design, or (ii) that per-thread bandwidth regulation is enforced. Such arbitration schemes provide timing guarantees, but make poor use of the memory bandwidth available in a modern HeSoC. Controlled Memory Request Injection (CMRI) is a recently-proposed bandwidth limitation concept that builds on top of a mutually-exclusive schedule but still allows the threads currently not entitled to access memory to use as much of the unused bandwidth as possible without losing the timing guarantee. CMRI has been discussed in the context of a multi-core CPU, but the same principle applies also to a more complex system such as an HeSoC. In this article, we introduce two CMRI schemes suitable for HeSoCs: Voluntary Throttling via code refactoring and Bandwidth Regulation via dynamic throttling. We extensively characterize a proof-of-concept incarnation of both schemes on two HeSoCs: an NVIDIA Tegra TX2 and a Xilinx UltraScale+, highlighting the benefits and the costs of CMRI for synthetic workloads that model worst-case DRAM access. We also test the effectiveness of CMRI with real benchmarks, studying the effect of interference among the host CPU and the accelerators
Novel methodologies for predictable CPU-to-GPU command offloading
No full textThere is an increasing industrial and academic interest towards a more predictable characterization
of real-time tasks on high-performance heterogeneous embedded platforms, where a host system
offloads parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing
Units (GP-GPUs). In this paper, we analyze an important aspect that has not yet been considered
in the real-time literature, and that may significantly affect real-time performance if not properly
treated, i.e., the time spent by the CPU for submitting GP-GPU operations. We will show that the
impact of CPU-to-GPU kernel submissions may be indeed relevant for typical real-time workloads,
and that it should be properly factored in when deriving an integrated schedulability analysis for
the considered platforms.
This is the case when an application is composed of many small and consecutive GPU compute/copy operations. While existing techniques mitigate this issue by batching kernel calls into a
reduced number of persistent kernel invocations, in this work we present and evaluate three other
approaches that are made possible by recently released versions of the NVIDIA CUDA GP-GPU
API, and by Vulkan, a novel open standard GPU API that allows an improved control of GPU command submissions. We will show that this added control may significantly improve the application
performance and predictability due to a substantial reduction in CPU-to-GPU driver interactions,
making Vulkan an interesting candidate for becoming the state-of-the-art API for heterogeneous
Real-Time systems.
Our findings are evaluated on a latest generation NVIDIA Jetson AGX Xavier embedded board,
executing typical workloads involving Deep Neural Networks of parameterized complexity
HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper)
No full textCurrent homogeneous and heterogeneous computing systems reach high performance through parallelization. Yet, parallel execution of tasks entails non-trivial latency-vs-throughput issues when it comes to concurrent accesses to shared memory. In this respect, effective bandwidth regulation solutions do exist, and provide a basic mechanism to control the latency of memory accesses. Such solutions, though, are often cumbersome to deploy and to configure to guarantee both bounded latency and high utilization of the memory bandwidth. The problem is that memory latency varies non-linearly with the number and type of concurrent accesses, and the latter may in turn vary with time, often unpredictably. For this reason, previous attempts at memory regulation in scheduling solutions resulted either in poor real-time execution guarantees, or in severe underutilization of the memory bandwidth. In this paper, we outline High Memory Bandwidth (HMB), a scheduling solution that guarantees bounded response times to real-time task sets through memory regulation, while also reaching a high utilization memory bandwidth. Since the complete solution is complex, just like the problem it addresses, this preliminary work defines in full detail only the core mechanism. This mechanism builds on the notion of memory access slowdown experienced by any processor performing back-to-back memory operations; this slowdown is due to the interference generated by other processors also accessing the memory at the same time. The core mechanism assumes that each processor can tolerate a certain amount of slowdown before the timing behavior of the task(s) it is running is compromised. Each processor has a priority assigned: the higher the priority, the more stringent the timing requirements. The slowdown can be controlled by regulating with precision the maximum amount of system bandwidth each processor is allowed to use, based on its priority. The proposed mechanism finds the maximum bandwidth each processor can use such that the highest number of processors simultaneously accessing memory is found (thus avoiding memory bandwidth underutilization) while guaranteeing that the slowdown of each processor is kept within the tolerated limits
Is the Optimal Implementation Inefficient? Elementarily Not
No full textSharing graphs are a local and asynchronous implementation of lambda-calculus beta-reduction (or linear logic proof-net cut-elimination) that avoids useless duplications. Empirical benchmarks suggest that they are one of the most efficient machineries, when one wants to fully exploit the higher-order features of lambda-calculus. However, we still lack confirming grounds with theoretical solidity to dispel uncertainties about the adoption of sharing graphs.
Aiming at analysing in detail the worst-case overhead cost of sharing operators, we restrict to the case of elementary and light linear logic, two subsystems with bounded computational complexity of multiplicative exponential linear logic. In these two cases, the bookkeeping component is unnecessary, and sharing graphs are simplified to the so-called "abstract algorithm". By a modular cost comparison over a syntactical simulation, we prove that the overhead of shared reductions is quadratically bounded to cost of the naive implementation, i.e. proof-net reduction. This result generalises and strengthens a previous complexity result, and implies that the price of sharing is negligible, if compared to the obtainable benefits on reductions requiring a large amount of duplication
API Comparison of CPU-To-GPU Command Offloading Latency on Embedded Platforms (Artifact)
No full textHigh-performance heterogeneous embedded platforms allow offloading of parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing Units (GP-GPUs). A time-predictable characterization of task submission is a must in real-time applications. We provide a profiler of the time spent by the CPU for submitting stereotypical GP-GPU workload shaped as a Deep Neural Network of parameterized complexity. The submission is performed using the latest API available: NVIDIA CUDA, including its various techniques, and Vulkan. Complete automation for the test on Jetson Xavier is also provided by scripts that install software dependencies, run the experiments, and collect results in a PDF report
Complex nature of Zygosaccharomyces wild strains: a genotypic and functional characterization
No full textGenotypic and functional characterization of Zygosaccharomyces wild strain
Novel Methodologies for Predictable CPU-To-GPU Command Offloading
No full textThere is an increasing industrial and academic interest towards a more predictable characterization of real-time tasks on high-performance heterogeneous embedded platforms, where a host system offloads parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing Units (GP-GPUs). In this paper, we analyze an important aspect that has not yet been considered in the real-time literature, and that may significantly affect real-time performance if not properly treated, i.e., the time spent by the CPU for submitting GP-GPU operations. We will show that the impact of CPU-to-GPU kernel submissions may be indeed relevant for typical real-time workloads, and that it should be properly factored in when deriving an integrated schedulability analysis for the considered platforms.
This is the case when an application is composed of many small and consecutive GPU compute/copy operations. While existing techniques mitigate this issue by batching kernel calls into a reduced number of persistent kernel invocations, in this work we present and evaluate three other approaches that are made possible by recently released versions of the NVIDIA CUDA GP-GPU API, and by Vulkan, a novel open standard GPU API that allows an improved control of GPU command submissions. We will show that this added control may significantly improve the application performance and predictability due to a substantial reduction in CPU-to-GPU driver interactions, making Vulkan an interesting candidate for becoming the state-of-the-art API for heterogeneous Real-Time systems.
Our findings are evaluated on a latest generation NVIDIA Jetson AGX Xavier embedded board, executing typical workloads involving Deep Neural Networks of parameterized complexity
