17 research outputs found
Virtual Nodes in Slurm
No full textHPC clusters are facing an increasing demand for resources from a wide range of workloads. Moreover, there is an increase in the type of workloads and thus their software- related requirements in HPC systems while isolation among different users remains indispensable. Virtual machines allows both isolation among different users and privileged access to a fully customizable software stack with very low performance overhead. In this work we introduce VINO-Slurm by extending Slurm for running jobs in virtual nodes or else, virtual machines
Prefetching and Cache Management using Task Lifetimes
No full textTask-based dataflow programming models and runtimes emerge as promising candidates for programming multicore and manycore architectures. These programming models analyze dynamically task dependencies at runtime and schedule independent tasks concurrently to the processing elements. In such models, cache locality, which is critical for performance, becomes more challenging in the presence of fine-grain tasks, and in architectures with many simple cores.This paper presents a combined hardware-software approach to improve cache locality and offer better performance is terms of execution time and energy in the memory system. We propose the explicit bulk prefetcher (EBP) and epoch-based cache management (ECM) to help runtimes prefetch task data and guide the replacement decisions in caches. The runtimem software can use this hardware support to expose its internal knowledge about the tasks to the architecture and achieve more efficient task-based execution. Our combined scheme outperforms HW-only prefetchers and state-of-the-art replacement policies, improves performance by an average of 17%, generates on average 26% fewer L2 misses, and consumes on average 28% less energy in the components of the memory system
ATLAS I: A Single-chip ATM switch for NOWs
No full text. Although ATM (Asynchronous Transfer Mode), is a widely accepted standard for WANs (Wide Area Networks), it has not yet been widely embraced by the NOW community, because (i) most current ATM switches (and interfaces) have high latency, and and (ii) they drop cells when (even short-term) congestion happens. In this paper, we present ATLAS I, a single-chip ATM switch with 20 Gbits/sec aggregate I/O throughput, that was designed to address the above concerns. ATLAS I provides sub-microsecond cut-through latency, and (optional) backpressure (credit-based) flow control which never drops ATM cells. The architecture of ATLAS I has been fully specified and the design of the chip is well under progress. ATLAS I will be fabricated by SGS Thomson, Crolles, France, in 0.5 ¯m CMOS technology. 1 Introduction Popular contemporary computing environments are comprised of powerful workstations connected via a high-speed network, giving rise to systems called workstation clusters or Networks of Worksta..
Affine-NoC: multi-ring NoCs exploiting long physical links
No full textRouterless multi-ring proposals are low-cost NoCs that employ multiple independent rings, avoiding any crossbars or arbitration mechanisms. Their complexity lies on the selection
of the set of rings to connect all the nodes. Previous proposals result in unbalanced designs with high hop counts. This work introduces Affine-NoC, a balanced routerless NoC based on a novel arrangement of rings derived from the Affine Plane. Affine-NoC exploits express channels to connect distant processing elements, allowing for a completely balanced layout of the set of rings and a reduction in average distance and diameter without sacrificing bisection bandwidth. Analysis shows that Affine-NoC presents a balanced design with a low number of rings per node and reduced complexity, similar cost to previous proposals in terms of aggregated link length, while it simplifies the multiplex units and reduces the hop count. Simulation results show that Affine-NoC reduces hop count and average latency by 76% and 20.5% respectively compared to previous designs, it reduces deflections by 27% and avoids unfairness, making it a feasible alternative for multi-ring routerless NoCs.This work is supported by RED-SEA, a project that receives funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 955776. The JU receives support from the European Union’s Horizon 2020 research and innovation programme of France, Greece, Germany, Spain (PCI2021-121934 and PCI2021-121976), Italy, Switzerland. This work is also supported by grants TED2021-131176B-I00 and PID2022-136454NB-C21 funded by MICIU/AEI/ 10.13039/501100011033 and by ERDF/EU
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
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Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures
No full textHeterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big. LITTLE architecture and show that the most efficient configuration is not always the expected one. We study the performance and energy tradeoffs of the big and the LITTLE ARM cores at different voltage and frequency levels. To do so we use various workloads and observe the overheads and benefits from using one configuration over another. Subsequently, we investigate how the workload characteristics and their execution on a particular core type affect energy consumption. We develop a lightweight energy model, suitable for runtime use, to accurately capture the above tradeoffs. Our model uses as input parameters only the instructions per cycle (IPC) and instruction mix. We evaluate the accuracy of the model across the two core types, different frequencies and various benchmarks. The model is able to predict the changes in the energy consumption of a program when moving from one configuration to another with an average error of 4.7%. Moreover, it is able to sort correctly 96% of the configurations across all benchmarks based on their energy consumption. Finally, our energy model can predict correctly for 22 out of 26 benchmarks the configuration that minimizes the energy-delay product (EDP); in the remaining four benchmarks the increase in EDP is less than 2.46%
Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms
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