1,721,327 research outputs found
Gate Current Noise in Ultrathin Oxide MOSFETs and Its Impact on the Performance of Analog Front-End Circuits
No full textIn future charged particle tracking systems, readout integrated circuits will be based on CMOS processes with minimum feature size in the 100 nm range. In nanoscale technologies, the reduction of the gate oxide thickness may lead to a non-negligible gate current due to direct tunneling phenomena. This leakage current, which is caused by discrete charges randomly crossing a potential barrier, yields an increase of the static power consumption for the digital section of the readout circuits and might degrade the noise performances of the analog front-end. As a consequence, in these advanced CMOS processes, an accurate characterization of the gate current noise is necessary in order to establish design criteria for detector analog front-end applications. This work presents the results of static and noise characterization of the gate-leakage current of NMOS devices belonging to a 90 nm commercial process. Data extracted from the measurements have been used to validate an analytical model for the gate current noise, which provides a useful tool for evaluating the impact of this noise source on the resolution limits achievable by low-noise charge amplifiers
Front-end electronics for pixel sensors
No full textThis paper discusses the criteria that underlie the design of front-end systems for pixel sensors of different types in a highly diversified fields of application. In the pixel front-end systems, low level analog signals coexist with digital activities and the design must comply with severe limitations in the area and in the power allotted to the single pixel cell. Noise and radiation hardness issues are of utmost importance in several applications. Some ways to arrive at a design which suits specific application requirements are discussed and the impact of the most advanced monolithic processes is evaluated. © 2001 Elsevier Science B.V
Design of a pixel readout processor for nano-meter resolution x-ray ptychography
No full textLe beamline ad alta luminosità sono state ampiamente utilizzate come sorgenti per la continua indagine sulla struttura della materia. Procedendo verso nuove generazioni di apparati a luce di sincrotrone, le specifiche sui rivelatori e sull'elettronica front-end a segnale misto sono diventate sempre più rigorose richiedendo studi dedicati e sfruttando ogni aspetto delle tecnologie dei circuiti integrati.
Nel presente lavoro di tesi verrà fornita un'introduzione sulle basi dell'interazione della radiazione con la materia e i sistemi basati su sincrotrone per introdurre la pitcografia a raggi x, l'applicazione target del circuito integrato sviluppato, pFREYA16. Il nucleo del lavoro sarà focalizzato sulla motivazione allo sviluppo di tale circuito, nel quadro di una collaborazione internazionale con l'Argonne National Laboratory (Chicago, IL, US) e l'Università di Pavia per lo sviluppo di un circuito di alte prestazioni, con una finestra di elaborazione di 1 MHz, su un rivelatore a pixel per applicazioni di pticografia a raggi x con risoluzione nanometrica, e sull'analisi di ciascun blocco analogico e digitale integrato nei chip prodotti, riportando simulazioni post-layout e considerazioni per ciascuno di essi.
L'ASIC è stato sviluppato con una tecnologia CMOS commerciale da 65 nm ed è un circuito di lettura a pixel composto da pixel a bassissimo rumore e bassa potenza. Nelle simulazioni post-layout, ogni pixel ha riportato una risoluzione di un singolo fotone, con una carica equivalente di rumore di 250 elettroni rms, un consumo di 220 μW/pixel e un intervallo dinamico di ingresso fino a 256 fotoni con tre diverse energie di fotoni: 5 keV, 9 keV e 25 keV. Ogni pixel è configurabile con tempo di integrazione variabile, quattro modalità per il CSA e quattro tempi di picco selezionabili. Integra inoltre una catena di rilevamento del "signal over threshold" per scartare i segnali indesiderati e un ADC SAR a 10 bit per digitalizzare l'output.High-luminosity beamlines have been used vastly as a source for the perpetual investigation of the structure of matter. Progressing towards new generations of light storage rings, the specifications on the detectors and front-end mixed-signal electronics have become more and more stringent requiring dedicated studies and exploiting every aspect of the integrated circuit technologies.
In the present thesis work an introduction to the basics of radiation interaction with matter and synchrotron systems will be provided to introduce x-ray ptychography, the target application of the developed application specific integrated circuit, pFREYA16. The core of the work will be focused on motivating the development of such a circuit, in a frame of an international collaboration with Argonne National Laboratory (Chicago, IL, US) and the University of Pavia for the development of a top-tier, 1-MHz frame, pixellated detector for nano-meter resolution x-ray ptychography applications, and on analysing each analog and digital block integrated into the produced chips, reporting post-layout simulations and considerations for each of them.
The ASIC has been developed in a commercial 65 nm CMOS technology and it is a pixellated readout circuit composed of very low noise and low power pixels. In post-layout simulations, each pixel has reported a single photon detection capability, with an equivalent noise charge of 250 electrons rms, power consumption of 220 μW/pixel, and an input dynamic range of up to 256 photons with three different photon energies: 5 keV, 9 keV, and 25 keV. Each pixel is configurable with variable integration time, four CSA modes, and four selectable peaking times. It also integrates a signal over threshold detection chain to reject unwanted signals and a 10-bit SAR ADC to digitise the output
Progetto e sviluppo dell’elettronica di lettura per il tracciatore Si(Li) dell'esperimento GAPS
No full textModeling I-MOS Capacitor C-V Characteristic for Non-Linear Charge Sensitive Amplifiers
No full textAn analytic model for the C-V characteristic of Inversion-Mode MOS (I-MOS) capacitors is defined, to be used in the design of Charge Sensitive Amplifiers (CSAs) with dynamic signal compression feature. The model is derived from the equations governing channel inversion in the two and four terminal metal-oxide-semiconductor structure. A comparison between the model predictions and the simulation results is provided for MOS capacitors and CSAs in a 65 nm CMOS technology
Radiation effects on the noise parameters of a 0.18 mu m CMOS technology for detector front-end applications
No full textThis paper presents a study of the effects of ionizing radiation on devices belonging to a 0.18 um CMOS process, in view of applications to the design of front-end integrated circuits for detectors in high energy physics experiments. Static, signal and noise performances of devices with various gate dimensions were monitored before and after exposure to gamma-rays from a 60Co source up to a 300 kGy(Si) total dose
Analog front-end design perspective of a 14 nm finFET technology
No full textN-and P-type transistors from a 14 nm finFET technology have been tested from the standpoint of static current-voltage characteristics, small signal parameters and noise properties in view of analog front-end applications. Device electrical features are found to be compliant with the scaling trend as carried on with planar CMOS technologies. Comparison with standard, less scaled bulk CMOS processes points out that transition from planar, single-gate to vertical, multiple-gate structures does not affect significantly the device analog performance. The paper will focus in particular on the noise properties of the transistors, featuring different gate length and width and operated in the weak to moderate inversion region
Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-um CMOS generation
No full textThis paper presents a study of the ionizing radiation tolerance of analog parameters of 0.18-um CMOS transistors, in view of the application to the design of front-end integrated circuits for detectors in high-energy physics experiments. Static, signal, and noise performances of devices with various gate dimensions were monitored before and after irradiation up to a 300-kGy(Si) total dose of 60 Co gamma-rays. Different device biasing conditions under irradiation were used, and the relevant results are discussed. A comparison with previous CMOS generations is carried out to evaluate the impact of device scaling on the radiation sensitivity
Performance of a high accuracy injection circuit for in-pixel calibration of a large sensor matrix
No full textThis work presents the experimental results from the characterization of a high accuracy injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel but, in principle, can be used also for other kinds of detectors, e. g. deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques can be provided by the circuit: one for a charge sensitive amplification and the other for a transresistance readout architecture. The aim of the paper is to describe the architecture of the calibration circuit and to present the results from the characterization of the system, which has been implemented in a 130 nm CMOS technology
Design, Testing and Calibration of the GAPS Experiment Si(Li) Tracker Readout ASIC: From the First Flight Campaign Toward the Second Mission Upgrade
No full textIl General Antiparticle Spectrometer è un esperimento a pallone stratosferico concepito per effettuare tre voli di lunga durata dall’Antartide, con l’obiettivo di ricercare antinuclei cosmici a bassa energia, in particolare antideuteroni, come canale indiretto per lo studio della materia oscura. La tecnica di rivelazione si basa sulla formazione e sul decadimento di atomi esotici, riconoscibili attraverso l’emissione di raggi x caratteristici e la successiva annichilazione in particelle secondarie. Al cuore dello strumento si trova il tracciatore al silicio, costituito da rivelatori al silicio drogati al litio, operati a –40°C e letti da un circuito integrato dedicato, denominato SLIDER32, realizzato in tecnologia CMOS a 180 nm. La tesi descrive le attività di integrazione, calibrazione e validazione dell’elettronica di lettura del tracciatore basata su SLIDER32. La caratterizzazione in laboratorio di un modulo del tracciatore, condotta con una sorgente di Americio-241 e con muoni cosmici, è stata affiancata da prove di calibrazione e test dell’intero tracciatore nella configurazione prevista per il primo volo, che hanno portato alla prima acquisizione di uno spettro a raggi x da una sorgente di Cadmio-109. Queste attività hanno fatto parte della fase di integrazione e test dell’esperimento, culminata con l’assemblaggio completo dello strumento e la sua validazione durante la campagna antartica del 2024. Sulla base di questa esperienza è stato progettato e realizzato un nuovo circuito integrato, sviluppato come evoluzione di SLIDER32: il chip ANTARES4, fabbricato in tecnologia CMOS a 65 nm. Il dispositivo integra otto canali analogici fino allo stadio di shaping e introduce soluzioni innovative per la compressione dinamica del segnale mediante transistori MOS a soglia dinamica, insieme a un circuito migliorato di compensazione della corrente di leakage all’ingresso del preamplificatore. La caratterizzazione di laboratorio ha fornito una prima validazione di queste soluzioni progettuali, ponendo le basi per il sistema di lettura di nuova generazione che sarà impiegato nel secondo volo dell’esperimento.The General Antiparticle Spectrometer is a balloon-borne experiment designed to perform three long-duration flights from Antarctica to search for low-energy cosmic antinuclei, in particular antideuterons, as an indirect probe of dark matter. Its detection method is based on the formation and decay of exotic atoms, identified through the emission of characteristic x-rays and the subsequent annihilation into secondary particles. At the core of the instrument is the silicon tracker, composed of lithium-drifted silicon detectors operated at −40°C and read out by a custom application-specific integrated circuit, SLIDER32, implemented in 180 nm CMOS technology. This thesis reports on the integration, calibration, and validation of the SLIDER32-based tracker readout electronics. Laboratory characterization of a single tracker module with an Americium-241 source and cosmic muons was complemented by calibration and testing of the full tracker in its flight configuration, leading to the first x-ray spectrum acquisition from a Cadmium-109 source. These activities formed part of the integration and testing phase of the experiment for the first flight, which culminated in the complete instrument assembly and validation during the Antarctic campaign of 2024. Building on this experience, the work introduces the design and characterization of a new prototype integrated circuit conceived as an upgrade to SLIDER32: the ANTARES4 chip, fabricated in 65 nm CMOS technology. The device integrates eight analog channels up to the shaping stage and implements innovative solutions for dynamic signal compression exploiting dynamic-threshold MOS transistors, together with an improved detector leakage current compensation circuit at the preamplifier input. Its laboratory characterization provides a first validation of these design choices, laying the foundations for the next-generation tracker readout system to be adopted in the second flight of the experiment
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