196,491 research outputs found
Qualification of a high-resolution on-chip injection circuit for the calibration of the DSSC X-ray imager for the European XFEL
No full textThe availability of on-chip sources with high degree of accuracy able to probe the response of the x-ray imaging detectors in all the conditions foreseen at the European XFEL is a key issue in order to implement automated procedures in order to trim gain and offset of each individual pixel channel to the desired target gain mode with the required degree of accuracy at the XFEL beamline/experiment.In the F2 readout ASIC of the DSSC instrument (DEPFET Sensor with Signal Compression) an improved 13 bit voltage DAC coupled to an electrical injection circuit has been implemented. A thorough measurement campaign to qualify the F2 DAC and the injected charge was conducted on a 64×64 miniSDD-F2 chip as a function of all relevant parameters
Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology
No full textThis paper presents a study of the ionizing radiation tolerance of 0.13 /spl mu/m CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with /sup 60/Co /spl gamma/-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations
Analog front-end design perspective of a 14 nm finFET technology
No full textN-and P-type transistors from a 14 nm finFET technology have been tested from the standpoint of static current-voltage characteristics, small signal parameters and noise properties in view of analog front-end applications. Device electrical features are found to be compliant with the scaling trend as carried on with planar CMOS technologies. Comparison with standard, less scaled bulk CMOS processes points out that transition from planar, single-gate to vertical, multiple-gate structures does not affect significantly the device analog performance. The paper will focus in particular on the noise properties of the transistors, featuring different gate length and width and operated in the weak to moderate inversion region
Radiation effects on the noise parameters of a 0.18um CMOS technology for detector front-end applications
No full textRadiation effects on the noise parameters of a 0.18 mu m CMOS technology for detector front-end applications
No full textThis paper presents a study of the effects of ionizing radiation on devices belonging to a 0.18 um CMOS process, in view of applications to the design of front-end integrated circuits for detectors in high energy physics experiments. Static, signal and noise performances of devices with various gate dimensions were monitored before and after exposure to gamma-rays from a 60Co source up to a 300 kGy(Si) total dose
Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configuration
No full textPixel-level charge and current injection circuit for high accuracy calibration of the dssc chip at the european xfel
No full textThis work presents the experimental results from the characterization of the second prototype of a high accuracy (in terms of linearity, mismatch and noise) injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel device, the DEPFET Sensor with Signal Compression (DSSC) chip, for the large format imager at the European X-ray Free Electron Laser (XFEL), but, in principle, it can be used also for other kinds of detectors, e.g., deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques have been investigated: one for a charge sensitive amplification and the other for a transresistance readout channel. The aim of the paper is to describe the architecture of the calibration circuit, which has been implemented in a 130-nm CMOS technology, and to present the results from the characterization of the second prototype. © 1963-2012 IEEE
0.13 um CMOS technologies for radiation hardness analog front-end circuits in LHC upgrades
No full textEvaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics
No full textTotal Ionizing Dose Effects on the Noise Performances of a 0.13 um CMOS Technology
No full textThis paper presents a study of the ionizing radiation tolerance of 0.13 um CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with 60Co  gamma-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations
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