1,721,546 research outputs found
Hybrid interconnect network for on-chip low-power clock distribution
No full textClock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with the CMOS technology shrinking, it becomes critical to deliver high-quality global clock signal with low propagation delay and hence conventional metallic interconnect seems to meet its bottleneck, as a clock distribution network (CDN) might consume up to 50% of the overall power. To address these problems, this Letter proposes a novel combination of wireless and conventional metallic interconnect to improve the performance of on-chip clock distribution. By incorporating integrated wireless clock transceivers and efficient modulation technique, overall performance has been increased significantly with a total delay reduction of 66.8% compared with a new cornerstone tapered H-tree model from 400 to 130 ps. In addition, clock uncertainties are now predictable according to the displacement of transceivers,,33 ps of clock skew at 2.5 GHz input with highly unbalanced loads could be found within the proposed CDN, and hence, indicates a promising potential of future high-performance on-chip clock distribution.</p
IP protection of mesh NoCs using square spiral routing
No full textIntellectual property (IP) core reuse is essential for the design process of system-on-chip (SoC). Network-on-chip (NoC) has been used as an independent IP core during SoC design. However, the NoC has not been protected via IP protection and paid attention on its innovations. This paper proposes the first known approach to protect the authorship and the usage legitimacy of NoCs using specially designed routing, square spiral routing. The special routing algorithm exploits routing redundancy inherent in the mesh NoCs and transports packets along the paths, which have very low probability to be taken under commonly used routing algorithms. These unique and diverse paths are exploited in this paper to embed information of the author and identify the legal buyer of NoCs, showing high robustness and credibility. The hardware implementation of an IP-protected mesh NoC shows that the area overhead is small, which is ~0.74%, and the power overhead is ~0.52%, while the functionality and performance of the network is not affected. In this paper, the approach is presented for the mesh NoC, but the idea is equally applicable to other NoC topologies where the unique and diverse paths also inherently exist
Clock calibration faults and their impact on quality of high performance microprocessors
No full textIn this paper we analyze the fault effects of some clock calibration features which are common to today's high performance microprocessors. We will show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g., scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that Very Deep Sub-Micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignored
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Network-on-chip multicast architectures using hybrid wire and surface-wave interconnects
No full textThe network-on-chip (NoC) has been introduced as an efficient communication backbone to tackle the increasing challenges of on-chip communication. Nevertheless, merely metalbased NoC implementation offers only limited performance and power scalability in terms of multicast and broadcast traffics. To meet scalability demands, this paper addresses the systemlevel challenges for intra-chip multicast communication in a proposed hybrid interconnects architecture. This hybrid NoC combines and utilizes both regular metal on-chip interconnects and new type of wireless-NoC (WiNoC) which is Zenneck surface wave interconnects (SWI). Moreover, this paper embeds novel multicast routing and arbitration schemes to address system-level multicast-challenges in the proposed architecture. Specifically, a design exploration of contention handling in SWI layer is considered in both centralized and decentralized manners. Consequently, the hybrid wire-SWI architecture avoids overloading the network, alleviates the formation of traffic hotspots and avoid deadlocks that are typically associated with state-of-theart multicast handling. The evaluation is based on a cycleaccurate simulation and hardware description. It demonstrates the effectiveness of the proposed architecture in terms of power consumption (up to around 10x) and performance (around 22x) compared to regular NoCs. These results are achieved with negligible hardware overheads. This study explore promising potential of the proposed architecture for current and future NoC-based many-core processors
An efficient runtime power allocation scheme for many-core systems inspired from auction theory
No full textDesign of future many-core chips is experiencing a paradigm shift to the so-called power-budgeting design, due to the widening gap between instantaneous power consumption and the allowed maximum power, referred as the power budget. Critical to these many-core chips is the runtime power allocation mechanism which can help optimizing the overall system performance under a limited power budget constraint. In this paper, the power allocation problem (i.e., maximizing the system performance under a power budget) is modeled by a combinatorial auction. The problem can be transformed to a knapsack problem and the optimal solution reaches a Walrasian equilibrium. To solve the problem efficiently in a decentralized way, a Hierarchal MultiAgent based Power allocation (HiMAP) method is proposed with an optimal bound. In HiMAP, tiles bid for the opportunity to become active based on the chip?s total power budget. Upon finishing an auction process, certain tiles will be power gated and/or frequency scaled according to the power allocation decision. Experimental results have confirmed that HiMAP can reduce the execution time by as much as 45% compared to four competing methods. The runtime overhead and cost of HiMAP are also small, which makes it scale well with many-core systems
ICOS, CD40, and lymphotoxin beta receptors signal sequentially and interdependently to initiate a germinal center reaction
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